Angel Pons | bbc99cf | 2020-04-04 18:51:23 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 2 | |
| 3 | #include <assert.h> |
Ricardo Quesada | 954df3d | 2021-08-10 17:10:14 -0700 | [diff] [blame] | 4 | #include <commonlib/bsd/bcd.h> |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 5 | #include <console/console.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 6 | #include <delay.h> |
Nico Huber | 0f2dd1e | 2017-08-01 14:02:40 +0200 | [diff] [blame] | 7 | #include <device/i2c_simple.h> |
David Hendricks | 3c4951e | 2015-01-12 14:08:10 -0800 | [diff] [blame] | 8 | #include <rtc.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 9 | #include <soc/rk808.h> |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 10 | #include <stdint.h> |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 11 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 12 | #if CONFIG_PMIC_BUS < 0 |
| 13 | #error "PMIC_BUS must be set in mainboard's Kconfig." |
| 14 | #endif |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 15 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 16 | #define RK808_ADDR 0x1b |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 17 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 18 | #define DCDC_EN 0x23 |
| 19 | #define LDO_EN 0x24 |
| 20 | #define BUCK1SEL 0x2f |
| 21 | #define BUCK4SEL 0x38 |
| 22 | #define LDO_ONSEL(i) (0x39 + 2 * i) |
| 23 | #define LDO_SLPSEL(i) (0x3a + 2 * i) |
| 24 | |
David Hendricks | 3c4951e | 2015-01-12 14:08:10 -0800 | [diff] [blame] | 25 | #define RTC_SECOND 0x00 |
| 26 | #define RTC_MINUTE 0x01 |
| 27 | #define RTC_HOUR 0x02 |
| 28 | #define RTC_DAY 0x03 |
| 29 | #define RTC_MONTH 0x04 |
| 30 | #define RTC_YEAR 0x05 |
| 31 | #define RTC_WEEKS 0x06 |
| 32 | #define RTC_CTRL 0x10 |
| 33 | #define RTC_STATUS 0x11 |
| 34 | |
| 35 | #define RTC_CTRL_STOP_RTC (1 << 0) |
| 36 | #define RTC_CTRL_GET_TIME (1 << 6) |
| 37 | #define RTC_CTRL_RTC_READSEL (1 << 7) |
| 38 | |
huang lin | 3704e69 | 2015-02-27 19:35:04 -0800 | [diff] [blame] | 39 | #define DCDC_UV_ACT 0x28 |
huang lin | 75f431a | 2015-01-23 14:48:42 +0800 | [diff] [blame] | 40 | #define DCDC_ILMAX 0x90 |
| 41 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 42 | static int rk808_read(uint8_t reg, uint8_t *value) |
| 43 | { |
| 44 | return i2c_readb(CONFIG_PMIC_BUS, RK808_ADDR, reg, value); |
| 45 | } |
| 46 | |
| 47 | static int rk808_write(uint8_t reg, uint8_t value) |
| 48 | { |
| 49 | return i2c_writeb(CONFIG_PMIC_BUS, RK808_ADDR, reg, value); |
| 50 | } |
| 51 | |
| 52 | static void rk808_clrsetbits(uint8_t reg, uint8_t clr, uint8_t set) |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 53 | { |
| 54 | uint8_t value; |
| 55 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 56 | if (rk808_read(reg, &value) || rk808_write(reg, (value & ~clr) | set)) |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 57 | printk(BIOS_ERR, "ERROR: Cannot set Rk808[%#x]!\n", reg); |
| 58 | } |
| 59 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 60 | void rk808_configure_switch(int sw, int enabled) |
Julius Werner | 8f3883d | 2014-09-26 21:01:08 -0700 | [diff] [blame] | 61 | { |
| 62 | assert(sw == 1 || sw == 2); |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 63 | rk808_clrsetbits(DCDC_EN, 1 << (sw + 4), !!enabled << (sw + 4)); |
Julius Werner | 8f3883d | 2014-09-26 21:01:08 -0700 | [diff] [blame] | 64 | } |
| 65 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 66 | void rk808_configure_ldo(int ldo, int millivolts) |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 67 | { |
| 68 | uint8_t vsel; |
| 69 | |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 70 | if (!millivolts) { |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 71 | rk808_clrsetbits(LDO_EN, 1 << (ldo - 1), 0); |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 72 | return; |
| 73 | } |
| 74 | |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 75 | switch (ldo) { |
| 76 | case 1: |
| 77 | case 2: |
| 78 | case 4: |
| 79 | case 5: |
| 80 | case 8: |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 81 | vsel = DIV_ROUND_UP(millivolts, 100) - 18; |
Julius Werner | ef639b2 | 2014-11-06 14:33:12 -0800 | [diff] [blame] | 82 | assert(vsel <= 0x10); |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 83 | break; |
| 84 | case 3: |
| 85 | case 6: |
| 86 | case 7: |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 87 | vsel = DIV_ROUND_UP(millivolts, 100) - 8; |
Julius Werner | ef639b2 | 2014-11-06 14:33:12 -0800 | [diff] [blame] | 88 | assert(vsel <= 0x11); |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 89 | break; |
| 90 | default: |
| 91 | die("Unknown LDO index!"); |
| 92 | } |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 93 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 94 | rk808_clrsetbits(LDO_ONSEL(ldo), 0x1f, vsel); |
| 95 | rk808_clrsetbits(LDO_EN, 0, 1 << (ldo - 1)); |
Julius Werner | 7a757c9 | 2014-09-10 19:37:15 -0700 | [diff] [blame] | 96 | } |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 97 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 98 | void rk808_configure_buck(int buck, int millivolts) |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 99 | { |
| 100 | uint8_t vsel; |
| 101 | uint8_t buck_reg; |
| 102 | |
| 103 | switch (buck) { |
| 104 | case 1: |
| 105 | case 2: |
huang lin | 75f431a | 2015-01-23 14:48:42 +0800 | [diff] [blame] | 106 | /* 25mV steps. base = 29 * 25mV = 725 */ |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 107 | vsel = (DIV_ROUND_UP(millivolts, 25) - 29) * 2 + 1; |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 108 | assert(vsel <= 0x3f); |
| 109 | buck_reg = BUCK1SEL + 4 * (buck - 1); |
| 110 | break; |
| 111 | case 4: |
Elyes HAOUAS | 6df3b64 | 2018-11-26 22:53:49 +0100 | [diff] [blame] | 112 | vsel = DIV_ROUND_UP(millivolts, 100) - 18; |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 113 | assert(vsel <= 0xf); |
| 114 | buck_reg = BUCK4SEL; |
| 115 | break; |
| 116 | default: |
huang lin | 75f431a | 2015-01-23 14:48:42 +0800 | [diff] [blame] | 117 | die("Unknown buck index!"); |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 118 | } |
huang lin | 75f431a | 2015-01-23 14:48:42 +0800 | [diff] [blame] | 119 | rk808_clrsetbits(DCDC_ILMAX, 0, 3 << ((buck - 1) * 2)); |
huang lin | 3704e69 | 2015-02-27 19:35:04 -0800 | [diff] [blame] | 120 | |
| 121 | /* undervoltage detection may be wrong, disable it */ |
| 122 | rk808_clrsetbits(DCDC_UV_ACT, 1 << (buck - 1), 0); |
| 123 | |
David Hendricks | 4d24421 | 2015-01-12 13:13:30 -0800 | [diff] [blame] | 124 | rk808_clrsetbits(buck_reg, 0x3f, vsel); |
| 125 | rk808_clrsetbits(DCDC_EN, 0, 1 << (buck - 1)); |
huang lin | 08884e3 | 2014-10-10 20:28:47 -0700 | [diff] [blame] | 126 | } |
David Hendricks | 3c4951e | 2015-01-12 14:08:10 -0800 | [diff] [blame] | 127 | |
| 128 | static void rk808rtc_stop(void) |
| 129 | { |
| 130 | rk808_clrsetbits(RTC_CTRL, RTC_CTRL_STOP_RTC, 0); |
| 131 | } |
| 132 | |
| 133 | static void rk808rtc_start(void) |
| 134 | { |
| 135 | rk808_clrsetbits(RTC_CTRL, 0, RTC_CTRL_STOP_RTC); |
| 136 | } |
| 137 | |
| 138 | int rtc_set(const struct rtc_time *time) |
| 139 | { |
| 140 | int ret = 0; |
| 141 | |
| 142 | /* RTC time can only be set when RTC is frozen */ |
| 143 | rk808rtc_stop(); |
| 144 | |
| 145 | ret |= rk808_write(RTC_SECOND, bin2bcd(time->sec)); |
| 146 | ret |= rk808_write(RTC_MINUTE, bin2bcd(time->min)); |
| 147 | ret |= rk808_write(RTC_HOUR, bin2bcd(time->hour)); |
| 148 | ret |= rk808_write(RTC_DAY, bin2bcd(time->mday)); |
| 149 | ret |= rk808_write(RTC_MONTH, bin2bcd(time->mon)); |
| 150 | ret |= rk808_write(RTC_YEAR, bin2bcd(time->year)); |
| 151 | |
| 152 | rk808rtc_start(); |
| 153 | return ret; |
| 154 | } |
| 155 | |
| 156 | int rtc_get(struct rtc_time *time) |
| 157 | { |
| 158 | uint8_t value; |
| 159 | int ret = 0; |
| 160 | |
| 161 | /* |
| 162 | * Set RTC_READSEL to cause reads to access shadow registers and |
| 163 | * transition GET_TIME from 0 to 1 to cause dynamic register content |
| 164 | * to be copied into shadow registers. This ensures a coherent reading |
| 165 | * of time values as we access each register using slow I2C transfers. |
| 166 | */ |
| 167 | rk808_clrsetbits(RTC_CTRL, RTC_CTRL_GET_TIME, 0); |
| 168 | rk808_clrsetbits(RTC_CTRL, 0, RTC_CTRL_GET_TIME | RTC_CTRL_RTC_READSEL); |
| 169 | |
Jeffy Chen | 9b2fe63 | 2016-12-23 15:05:11 +0800 | [diff] [blame] | 170 | /* |
| 171 | * After we set the GET_TIME bit, the rtc time can't be read |
| 172 | * immediately. So we should wait up to 31.25 us. |
| 173 | */ |
| 174 | udelay(32); |
| 175 | |
David Hendricks | 3c4951e | 2015-01-12 14:08:10 -0800 | [diff] [blame] | 176 | ret |= rk808_read(RTC_SECOND, &value); |
| 177 | time->sec = bcd2bin(value & 0x7f); |
| 178 | |
| 179 | ret |= rk808_read(RTC_MINUTE, &value); |
| 180 | time->min = bcd2bin(value & 0x7f); |
| 181 | |
| 182 | ret |= rk808_read(RTC_HOUR, &value); |
| 183 | time->hour = bcd2bin(value & 0x3f); |
| 184 | |
| 185 | ret |= rk808_read(RTC_DAY, &value); |
| 186 | time->mday = bcd2bin(value & 0x3f); |
| 187 | |
| 188 | ret |= rk808_read(RTC_MONTH, &value); |
| 189 | time->mon = bcd2bin(value & 0x1f); |
| 190 | |
| 191 | ret |= rk808_read(RTC_YEAR, &value); |
| 192 | time->year = bcd2bin(value); |
| 193 | |
Martin Roth | a7a9c46 | 2016-07-26 09:03:25 -0600 | [diff] [blame] | 194 | time->wday = -1; /* unknown */ |
| 195 | |
David Hendricks | 3c4951e | 2015-01-12 14:08:10 -0800 | [diff] [blame] | 196 | return ret; |
| 197 | } |