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Martin Roth239b5df2022-07-26 22:18:26 -06001/* SPDX-License-Identifier: GPL-2.0-only */
2
Eric Biedermanc84c1902004-10-14 20:13:01 +00003#ifndef CPU_AMD_MTRR_H
4#define CPU_AMD_MTRR_H
5
Elyes HAOUASd35c7fe2018-10-30 07:07:00 +01006#define MTRR_IORR0_BASE 0xC0010016
7#define MTRR_IORR0_MASK 0xC0010017
8#define MTRR_IORR1_BASE 0xC0010018
9#define MTRR_IORR1_MASK 0xC0010019
Eric Biedermanc84c1902004-10-14 20:13:01 +000010
11#define MTRR_READ_MEM (1 << 4)
12#define MTRR_WRITE_MEM (1 << 3)
13
14#define SYSCFG_MSR 0xC0010010
Scott Duplichanf3cce2f2010-11-13 19:07:59 +000015#define SYSCFG_MSR_TOM2WB (1 << 22)
Eric Biedermanc84c1902004-10-14 20:13:01 +000016#define SYSCFG_MSR_TOM2En (1 << 21)
17#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
18#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
19#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
20#define SYSCFG_MSR_UcLockEn (1 << 17)
21#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
22#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
23#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
24#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
25#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
26#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
27#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
28
Warren Turkal4ffde942010-10-12 06:13:40 +000029#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
30#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
31
Kyösti Mälkki0127c6c2015-03-05 14:35:04 +020032#if defined(__ASSEMBLER__)
33#define TOP_MEM 0xC001001A
34#define TOP_MEM2 0xC001001D
35#else
36#define TOP_MEM 0xC001001Aul
37#define TOP_MEM2 0xC001001Dul
efdesign9878834b72011-08-04 16:18:16 -060038#endif
Eric Biedermanc84c1902004-10-14 20:13:01 +000039
40#define TOP_MEM_MASK 0x007fffff
41#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
42
Arthur Heymans1cb9cd52019-11-28 16:05:08 +010043#if !defined(__ASSEMBLER__)
Kyösti Mälkki4607cac2016-12-06 14:14:19 +020044
45#include <cpu/x86/msr.h>
Elyes HAOUAS5817c562020-07-12 09:03:22 +020046#include <stdint.h>
Kyösti Mälkki4607cac2016-12-06 14:14:19 +020047
Kyösti Mälkki17bb2252017-04-19 19:55:54 +030048struct device;
49void add_uma_resource_below_tolm(struct device *nb, int idx);
Kyösti Mälkkidbc47392012-08-05 12:11:40 +030050
Aaron Durbin75a62e72018-09-13 02:10:45 -060051static __always_inline msr_t rdmsr_amd(unsigned int index)
Kyösti Mälkki190011e2013-03-25 12:48:49 +020052{
53 msr_t result;
54 __asm__ __volatile__ (
55 "rdmsr"
56 : "=a" (result.lo), "=d" (result.hi)
57 : "c"(index), "D"(0x9c5a203a)
58 );
59 return result;
60}
61
Aaron Durbin75a62e72018-09-13 02:10:45 -060062static __always_inline void wrmsr_amd(unsigned int index, msr_t msr)
Kyösti Mälkki190011e2013-03-25 12:48:49 +020063{
64 __asm__ __volatile__ (
65 "wrmsr"
66 : /* No outputs */
67 : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
68 );
69}
70
Arthur Heymansc4350382021-10-28 12:35:39 +020071static inline uint64_t amd_topmem(void)
72{
73 return rdmsr(TOP_MEM).lo;
74}
75
76static inline uint64_t amd_topmem2(void)
77{
78 msr_t msr = rdmsr(TOP_MEM2);
79 return (uint64_t)msr.hi << 32 | msr.lo;
80}
Stefan Reinauer35b6bbb2010-03-28 21:26:54 +000081#endif
Eric Biedermanc84c1902004-10-14 20:13:01 +000082
83#endif /* CPU_AMD_MTRR_H */