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Eric Biedermanc84c1902004-10-14 20:13:01 +00001#ifndef CPU_AMD_MTRR_H
2#define CPU_AMD_MTRR_H
3
4#define IORR_FIRST 0xC0010016
5#define IORR_LAST 0xC0010019
6
7#define MTRR_READ_MEM (1 << 4)
8#define MTRR_WRITE_MEM (1 << 3)
9
10#define SYSCFG_MSR 0xC0010010
Scott Duplichanf3cce2f2010-11-13 19:07:59 +000011#define SYSCFG_MSR_TOM2WB (1 << 22)
Eric Biedermanc84c1902004-10-14 20:13:01 +000012#define SYSCFG_MSR_TOM2En (1 << 21)
13#define SYSCFG_MSR_MtrrVarDramEn (1 << 20)
14#define SYSCFG_MSR_MtrrFixDramModEn (1 << 19)
15#define SYSCFG_MSR_MtrrFixDramEn (1 << 18)
16#define SYSCFG_MSR_UcLockEn (1 << 17)
17#define SYSCFG_MSR_ChxToDirtyDis (1 << 16)
18#define SYSCFG_MSR_ClVicBlkEn (1 << 11)
19#define SYSCFG_MSR_SetDirtyEnO (1 << 10)
20#define SYSCFG_MSR_SetDirtyEnS (1 << 9)
21#define SYSCFG_MSR_SetDirtyEnE (1 << 8)
22#define SYSCFG_MSR_SysVicLimitMask ((1 << 8) - (1 << 5))
23#define SYSCFG_MSR_SysAckLimitMask ((1 << 5) - (1 << 0))
24
Warren Turkal4ffde942010-10-12 06:13:40 +000025#define IORRBase_MSR(reg) (0xC0010016 + 2 * (reg))
26#define IORRMask_MSR(reg) (0xC0010016 + 2 * (reg) + 1)
27
28#define TOP_MEM_MSR 0xC001001A
29#define TOP_MEM2_MSR 0xC001001D
efdesign9878834b72011-08-04 16:18:16 -060030#ifndef TOP_MEM
31 #define TOP_MEM TOP_MEM_MSR
32#endif
33#ifndef TOP_MEM2
34 #define TOP_MEM2 TOP_MEM2_MSR
35#endif
Eric Biedermanc84c1902004-10-14 20:13:01 +000036
37#define TOP_MEM_MASK 0x007fffff
38#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
39
Stefan Reinauer61aee5f2011-04-10 04:15:23 +000040#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__)
Eric Biedermanc84c1902004-10-14 20:13:01 +000041void amd_setup_mtrrs(void);
Kyösti Mälkkidbc47392012-08-05 12:11:40 +030042
43/* To distribute topmem MSRs to APs. */
44void setup_bsp_ramtop(void);
45uint64_t bsp_topmem(void);
46uint64_t bsp_topmem2(void);
Stefan Reinauer35b6bbb2010-03-28 21:26:54 +000047#endif
Eric Biedermanc84c1902004-10-14 20:13:01 +000048
49#endif /* CPU_AMD_MTRR_H */