bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 Tyan |
| 5 | * Copyright (C) 2006 AMD |
| 6 | * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. |
| 7 | * |
| 8 | * Copyright (C) 2006 MSI |
| 9 | * Written by bxshi <bingxunshi@gmail.com> for MSI. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 24 | */ |
| 25 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 26 | #define RAMINIT_SYSINFO 1 |
| 27 | #define CACHE_AS_RAM_ADDRESS_DEBUG 0 |
| 28 | |
| 29 | #define SET_NB_CFG_54 1 |
| 30 | |
| 31 | //used by raminit |
| 32 | #define QRANK_DIMM_SUPPORT 1 |
| 33 | |
| 34 | //used by incoherent_ht |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 35 | //#define K8_ALLOCATE_IO_RANGE 1 |
| 36 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 37 | //used by init_cpus and fidvid |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 38 | #define SET_FIDVID 1 |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 39 | //if we want to wait for core1 done before DQS training, set it to 0 |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 40 | #define SET_FIDVID_CORE0_ONLY 1 |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 41 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 42 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 43 | #include <string.h> |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 44 | #include <device/pci_def.h> |
| 45 | #include <device/pci_ids.h> |
| 46 | #include <arch/io.h> |
| 47 | #include <device/pnp_def.h> |
| 48 | #include <arch/romcc_io.h> |
| 49 | #include <cpu/x86/lapic.h> |
| 50 | #include "option_table.h" |
| 51 | #include "pc80/mc146818rtc_early.c" |
| 52 | #include "pc80/serial.c" |
Stefan Reinauer | 5a1f597 | 2010-03-31 14:34:40 +0000 | [diff] [blame] | 53 | #include "console/console.c" |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 54 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 55 | #include <cpu/amd/model_fxx_rev.h> |
| 56 | #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" |
| 57 | #include "northbridge/amd/amdk8/raminit.h" |
| 58 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 59 | #include "lib/delay.c" |
Stefan Reinauer | c51dc44 | 2010-04-07 01:44:04 +0000 | [diff] [blame] | 60 | #include <reset.h> |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 61 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 62 | #include "cpu/x86/lapic/boot_cpu.c" |
| 63 | #include "northbridge/amd/amdk8/reset_test.c" |
| 64 | #include "northbridge/amd/amdk8/debug.c" |
| 65 | #include "superio/nsc/pc87417/pc87417_early_serial.c" |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 66 | #include "cpu/x86/mtrr/earlymtrr.c" |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 67 | #include "cpu/x86/bist.h" |
| 68 | |
| 69 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 70 | |
| 71 | #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) |
| 72 | #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) |
| 73 | #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 74 | |
| 75 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 76 | { |
| 77 | } |
| 78 | |
| 79 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 80 | { |
| 81 | #define SMBUS_SWITCH1 0x70 |
| 82 | #define SMBUS_SWITCH2 0x72 |
| 83 | unsigned device = (ctrl->channel0[0]) >> 8; |
| 84 | smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); |
| 85 | smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); |
| 86 | } |
| 87 | |
| 88 | #if 0 |
| 89 | static inline void change_i2c_mux(unsigned device) |
| 90 | { |
| 91 | #define SMBUS_SWITCH1 0x70 |
| 92 | #define SMBUS_SWITCH2 0x72 |
| 93 | smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); |
| 94 | smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); |
| 95 | } |
| 96 | #endif |
| 97 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 98 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 99 | { |
| 100 | return smbus_read_byte(device, address); |
| 101 | } |
| 102 | |
| 103 | #include "northbridge/amd/amdk8/amdk8_f.h" |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 104 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame^] | 105 | #include "northbridge/amd/amdk8/coherent_ht.c" |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 106 | #include "northbridge/amd/amdk8/raminit_f.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 107 | #include "lib/generic_sdram.c" |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 108 | |
| 109 | /* msi does not want the default */ |
| 110 | #include "resourcemap.c" |
| 111 | |
| 112 | #include "cpu/amd/dualcore/dualcore.c" |
| 113 | |
| 114 | #define RC0 (0x10<<8) |
| 115 | #define RC1 (0x01<<8) |
| 116 | |
| 117 | #define DIMM0 0x50 |
| 118 | #define DIMM1 0x51 |
| 119 | #define DIMM2 0x52 |
| 120 | #define DIMM3 0x53 |
| 121 | #define DIMM4 0x54 |
| 122 | #define DIMM5 0x55 |
| 123 | #define DIMM6 0x56 |
| 124 | #define DIMM7 0x57 |
| 125 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 126 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 127 | |
| 128 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 129 | |
| 130 | #include "cpu/amd/model_fxx/fidvid.c" |
| 131 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 132 | #include "northbridge/amd/amdk8/early_ht.c" |
| 133 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 134 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 135 | { |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 136 | static const uint16_t spd_addr[] = { |
| 137 | //first node |
| 138 | RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, |
| 139 | RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 140 | //second node |
| 141 | RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, |
| 142 | RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 143 | }; |
| 144 | |
Stefan Reinauer | c51dc44 | 2010-04-07 01:44:04 +0000 | [diff] [blame] | 145 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + |
| 146 | CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 147 | |
| 148 | int needs_reset; |
| 149 | unsigned bsp_apicid = 0; |
| 150 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 151 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | 776b85b | 2010-03-18 16:18:58 +0000 | [diff] [blame] | 152 | /* Nothing special needs to be done to find bus 0 */ |
| 153 | /* Allow the HT devices to be found */ |
| 154 | |
| 155 | enumerate_ht_chain(); |
| 156 | |
| 157 | bcm5785_enable_rom(); |
| 158 | |
| 159 | bcm5785_enable_lpc(); |
| 160 | |
| 161 | //enable RTC |
| 162 | pc87417_enable_dev(RTC_DEV); |
| 163 | } |
| 164 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 165 | if (bist == 0) { |
| 166 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 167 | } |
| 168 | |
| 169 | // post_code(0x32); |
| 170 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 171 | pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 172 | uart_init(); |
| 173 | console_init(); |
| 174 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 175 | // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 176 | |
| 177 | /* Halt if there was a built in self test failure */ |
| 178 | report_bist_failure(bist); |
| 179 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 180 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 181 | |
| 182 | setup_ms9185_resource_map(); |
| 183 | #if 0 |
| 184 | dump_pci_device(PCI_DEV(0, 0x18, 0)); |
| 185 | dump_pci_device(PCI_DEV(0, 0x19, 0)); |
| 186 | #endif |
| 187 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 188 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 189 | |
| 190 | setup_coherent_ht_domain(); |
| 191 | |
| 192 | wait_all_core0_started(); |
| 193 | #if CONFIG_LOGICAL_CPUS==1 |
| 194 | // It is said that we should start core1 after all core0 launched |
| 195 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 196 | * So here need to make sure last core0 is started, esp for two way system, |
| 197 | * (there may be apic id conflicts in that case) |
| 198 | */ |
| 199 | start_other_cores(); |
| 200 | //bx_a010- wait_all_other_cores_started(bsp_apicid); |
| 201 | #endif |
| 202 | |
| 203 | /* it will set up chains and store link pair for optimization later */ |
| 204 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 205 | |
| 206 | bcm5785_early_setup(); |
| 207 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 208 | #if 0 |
| 209 | //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. |
| 210 | needs_reset = optimize_link_coherent_ht(); |
| 211 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 212 | #endif |
| 213 | |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 214 | #if SET_FIDVID == 1 |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 215 | |
| 216 | { |
| 217 | msr_t msr; |
| 218 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 219 | print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 220 | |
| 221 | } |
| 222 | |
| 223 | enable_fid_change(); |
| 224 | |
| 225 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 226 | |
| 227 | init_fidvid_bsp(bsp_apicid); |
| 228 | |
| 229 | // show final fid and vid |
| 230 | { |
| 231 | msr_t msr; |
| 232 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 233 | print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 234 | |
| 235 | } |
| 236 | #endif |
| 237 | |
| 238 | #if 1 |
| 239 | needs_reset = optimize_link_coherent_ht(); |
| 240 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 241 | |
| 242 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 243 | if (needs_reset) { |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 244 | print_info("ht reset -\n"); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 245 | soft_reset(); |
| 246 | } |
| 247 | #endif |
| 248 | allow_all_aps_stop(bsp_apicid); |
| 249 | |
| 250 | //It's the time to set ctrl in sysinfo now; |
| 251 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 252 | |
| 253 | enable_smbus(); |
| 254 | |
| 255 | #if 0 |
| 256 | int i; |
| 257 | for(i=0;i<2;i++) { |
| 258 | activate_spd_rom(sysinfo->ctrl+i); |
| 259 | dump_smbus_registers(); |
| 260 | } |
| 261 | #endif |
| 262 | |
| 263 | #if 0 |
| 264 | int i; |
| 265 | for(i=1;i<256;i<<=1) { |
| 266 | change_i2c_mux(i); |
| 267 | dump_smbus_registers(); |
| 268 | } |
| 269 | #endif |
| 270 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 271 | //do we need apci timer, tsc...., only debug need it for better output |
| 272 | /* all ap stopped? */ |
| 273 | // init_timer(); // Need to use TMICT to synconize FID/VID |
| 274 | |
| 275 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 276 | |
| 277 | #if 0 |
| 278 | print_pci_devices(); |
| 279 | #endif |
| 280 | |
| 281 | #if 0 |
| 282 | // dump_pci_devices(); |
| 283 | dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); |
| 284 | dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); |
| 285 | #endif |
| 286 | |
| 287 | post_cache_as_ram(); |
| 288 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 289 | } |
Stefan Reinauer | 798ef28 | 2010-03-29 22:08:01 +0000 | [diff] [blame] | 290 | |