commit 0867062412dd4bfe5a556e5f3fd85ba5b682d79b
author Stefan Reinauer <stepan@coresystems.de> Tue Jun 30 15:17:49 2009 +0000
committer Stefan Reinauer <stepan@openbios.org> Tue Jun 30 15:17:49 2009 +0000
tree 81ca5db12b8567b48daaa23a541bfb8a5dc011f8
parent 9702b6bf7ec5a4fb16934f1cf2724480e2460c89

This patch unifies the use of config options in v2 to all start with CONFIG_

It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/msi/ms9185/cache_as_ram_auto.c

diff --git a/src/mainboard/msi/ms9185/cache_as_ram_auto.c b/src/mainboard/msi/ms9185/cache_as_ram_auto.c
index cd7a3d2..aaedd63 100644
--- a/src/mainboard/msi/ms9185/cache_as_ram_auto.c
+++ b/src/mainboard/msi/ms9185/cache_as_ram_auto.c
@@ -157,7 +157,7 @@
 
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 #include "northbridge/amd/amdk8/early_ht.c"
 
@@ -215,7 +215,7 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
        failover_process(bist, cpu_init_detectedx);
 #endif
        real_main(bist, cpu_init_detectedx);
@@ -236,7 +236,7 @@
 
        };
 
-       struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
         int needs_reset;
         unsigned bsp_apicid = 0;
@@ -247,11 +247,11 @@
 
 //     post_code(0x32);
 
-       pc87417_enable_serial(SERIAL_DEV, TTYS0_BASE);
+       pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
-//     dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
+//     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);