bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 Tyan |
| 5 | * Copyright (C) 2006 AMD |
| 6 | * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. |
| 7 | * |
| 8 | * Copyright (C) 2006 MSI |
| 9 | * Written by bxshi <bingxunshi@gmail.com> for MSI. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 24 | */ |
| 25 | |
| 26 | #define ASSEMBLY 1 |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 27 | #define __PRE_RAM__ |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 28 | |
| 29 | #define RAMINIT_SYSINFO 1 |
| 30 | #define CACHE_AS_RAM_ADDRESS_DEBUG 0 |
| 31 | |
| 32 | #define SET_NB_CFG_54 1 |
| 33 | |
| 34 | //used by raminit |
| 35 | #define QRANK_DIMM_SUPPORT 1 |
| 36 | |
| 37 | //used by incoherent_ht |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 38 | //#define K8_ALLOCATE_IO_RANGE 1 |
| 39 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 40 | //used by init_cpus and fidvid |
| 41 | #define K8_SET_FIDVID 1 |
| 42 | //if we want to wait for core1 done before DQS training, set it to 0 |
| 43 | #define K8_SET_FIDVID_CORE0_ONLY 1 |
| 44 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 45 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 46 | #include <string.h> |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 47 | #include <device/pci_def.h> |
| 48 | #include <device/pci_ids.h> |
| 49 | #include <arch/io.h> |
| 50 | #include <device/pnp_def.h> |
| 51 | #include <arch/romcc_io.h> |
| 52 | #include <cpu/x86/lapic.h> |
| 53 | #include "option_table.h" |
| 54 | #include "pc80/mc146818rtc_early.c" |
| 55 | #include "pc80/serial.c" |
| 56 | #include "arch/i386/lib/console.c" |
| 57 | |
| 58 | #if 0 |
| 59 | static void post_code(uint8_t value) { |
| 60 | #if 1 |
| 61 | int i; |
| 62 | for(i=0;i<0x80000;i++) { |
| 63 | outb(value, 0x80); |
| 64 | } |
| 65 | #endif |
| 66 | } |
| 67 | #endif |
| 68 | |
| 69 | #include <cpu/amd/model_fxx_rev.h> |
| 70 | #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" |
| 71 | #include "northbridge/amd/amdk8/raminit.h" |
| 72 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 73 | #include "lib/delay.c" |
| 74 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 75 | |
| 76 | #include "cpu/x86/lapic/boot_cpu.c" |
| 77 | #include "northbridge/amd/amdk8/reset_test.c" |
| 78 | #include "northbridge/amd/amdk8/debug.c" |
| 79 | #include "superio/nsc/pc87417/pc87417_early_serial.c" |
| 80 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 81 | #include "cpu/x86/bist.h" |
| 82 | |
| 83 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 84 | |
| 85 | #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) |
| 86 | #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) |
| 87 | #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" |
| 88 | static void memreset_setup(void) |
| 89 | { |
| 90 | } |
| 91 | |
| 92 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 93 | { |
| 94 | } |
| 95 | |
| 96 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 97 | { |
| 98 | #define SMBUS_SWITCH1 0x70 |
| 99 | #define SMBUS_SWITCH2 0x72 |
| 100 | unsigned device = (ctrl->channel0[0]) >> 8; |
| 101 | smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); |
| 102 | smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); |
| 103 | } |
| 104 | |
| 105 | #if 0 |
| 106 | static inline void change_i2c_mux(unsigned device) |
| 107 | { |
| 108 | #define SMBUS_SWITCH1 0x70 |
| 109 | #define SMBUS_SWITCH2 0x72 |
| 110 | smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); |
| 111 | smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); |
| 112 | } |
| 113 | #endif |
| 114 | |
| 115 | |
| 116 | |
| 117 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 118 | { |
| 119 | return smbus_read_byte(device, address); |
| 120 | } |
| 121 | |
| 122 | #include "northbridge/amd/amdk8/amdk8_f.h" |
| 123 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 124 | |
| 125 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 126 | |
| 127 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 128 | |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 129 | #include "lib/generic_sdram.c" |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 130 | |
| 131 | /* msi does not want the default */ |
| 132 | #include "resourcemap.c" |
| 133 | |
| 134 | #include "cpu/amd/dualcore/dualcore.c" |
| 135 | |
| 136 | #define RC0 (0x10<<8) |
| 137 | #define RC1 (0x01<<8) |
| 138 | |
| 139 | #define DIMM0 0x50 |
| 140 | #define DIMM1 0x51 |
| 141 | #define DIMM2 0x52 |
| 142 | #define DIMM3 0x53 |
| 143 | #define DIMM4 0x54 |
| 144 | #define DIMM5 0x55 |
| 145 | #define DIMM6 0x56 |
| 146 | #define DIMM7 0x57 |
| 147 | |
| 148 | |
| 149 | #include "cpu/amd/car/copy_and_run.c" |
| 150 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 151 | |
| 152 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 153 | |
| 154 | #include "cpu/amd/model_fxx/fidvid.c" |
| 155 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 156 | #include "northbridge/amd/amdk8/early_ht.c" |
| 157 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 158 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 159 | { |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 160 | static const uint16_t spd_addr[] = { |
| 161 | //first node |
| 162 | RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, |
| 163 | RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, |
| 164 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 165 | //second node |
| 166 | RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, |
| 167 | RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, |
| 168 | #endif |
| 169 | |
| 170 | }; |
| 171 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 172 | struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 173 | |
| 174 | int needs_reset; |
| 175 | unsigned bsp_apicid = 0; |
| 176 | |
Patrick Georgi | 776b85b | 2010-03-18 16:18:58 +0000 | [diff] [blame^] | 177 | if (!((cpu_init_detectedx) || (!boot_cpu()))) { |
| 178 | /* Nothing special needs to be done to find bus 0 */ |
| 179 | /* Allow the HT devices to be found */ |
| 180 | |
| 181 | enumerate_ht_chain(); |
| 182 | |
| 183 | bcm5785_enable_rom(); |
| 184 | |
| 185 | bcm5785_enable_lpc(); |
| 186 | |
| 187 | //enable RTC |
| 188 | pc87417_enable_dev(RTC_DEV); |
| 189 | } |
| 190 | |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 191 | if (bist == 0) { |
| 192 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 193 | } |
| 194 | |
| 195 | // post_code(0x32); |
| 196 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 197 | pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 198 | uart_init(); |
| 199 | console_init(); |
| 200 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 201 | // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 202 | |
| 203 | /* Halt if there was a built in self test failure */ |
| 204 | report_bist_failure(bist); |
| 205 | |
| 206 | print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); |
| 207 | |
| 208 | setup_ms9185_resource_map(); |
| 209 | #if 0 |
| 210 | dump_pci_device(PCI_DEV(0, 0x18, 0)); |
| 211 | dump_pci_device(PCI_DEV(0, 0x19, 0)); |
| 212 | #endif |
| 213 | |
| 214 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); |
| 215 | |
| 216 | setup_coherent_ht_domain(); |
| 217 | |
| 218 | wait_all_core0_started(); |
| 219 | #if CONFIG_LOGICAL_CPUS==1 |
| 220 | // It is said that we should start core1 after all core0 launched |
| 221 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 222 | * So here need to make sure last core0 is started, esp for two way system, |
| 223 | * (there may be apic id conflicts in that case) |
| 224 | */ |
| 225 | start_other_cores(); |
| 226 | //bx_a010- wait_all_other_cores_started(bsp_apicid); |
| 227 | #endif |
| 228 | |
| 229 | /* it will set up chains and store link pair for optimization later */ |
| 230 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 231 | |
| 232 | bcm5785_early_setup(); |
| 233 | |
| 234 | |
| 235 | #if 0 |
| 236 | //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. |
| 237 | needs_reset = optimize_link_coherent_ht(); |
| 238 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 239 | #endif |
| 240 | |
| 241 | #if K8_SET_FIDVID == 1 |
| 242 | |
| 243 | { |
| 244 | msr_t msr; |
| 245 | msr=rdmsr(0xc0010042); |
| 246 | print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); |
| 247 | |
| 248 | } |
| 249 | |
| 250 | enable_fid_change(); |
| 251 | |
| 252 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 253 | |
| 254 | init_fidvid_bsp(bsp_apicid); |
| 255 | |
| 256 | // show final fid and vid |
| 257 | { |
| 258 | msr_t msr; |
| 259 | msr=rdmsr(0xc0010042); |
| 260 | print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); |
| 261 | |
| 262 | } |
| 263 | #endif |
| 264 | |
| 265 | #if 1 |
| 266 | needs_reset = optimize_link_coherent_ht(); |
| 267 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 268 | |
| 269 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 270 | if (needs_reset) { |
| 271 | print_info("ht reset -\r\n"); |
| 272 | soft_reset(); |
| 273 | } |
| 274 | #endif |
| 275 | allow_all_aps_stop(bsp_apicid); |
| 276 | |
| 277 | //It's the time to set ctrl in sysinfo now; |
| 278 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 279 | |
| 280 | enable_smbus(); |
| 281 | |
| 282 | #if 0 |
| 283 | int i; |
| 284 | for(i=0;i<2;i++) { |
| 285 | activate_spd_rom(sysinfo->ctrl+i); |
| 286 | dump_smbus_registers(); |
| 287 | } |
| 288 | #endif |
| 289 | |
| 290 | #if 0 |
| 291 | int i; |
| 292 | for(i=1;i<256;i<<=1) { |
| 293 | change_i2c_mux(i); |
| 294 | dump_smbus_registers(); |
| 295 | } |
| 296 | #endif |
| 297 | |
| 298 | memreset_setup(); |
| 299 | |
| 300 | //do we need apci timer, tsc...., only debug need it for better output |
| 301 | /* all ap stopped? */ |
| 302 | // init_timer(); // Need to use TMICT to synconize FID/VID |
| 303 | |
| 304 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 305 | |
| 306 | #if 0 |
| 307 | print_pci_devices(); |
| 308 | #endif |
| 309 | |
| 310 | #if 0 |
| 311 | // dump_pci_devices(); |
| 312 | dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); |
| 313 | dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); |
| 314 | #endif |
| 315 | |
| 316 | post_cache_as_ram(); |
| 317 | |
| 318 | |
| 319 | } |