bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame^] | 2 | * This file is part of the coreboot project. |
bxshi | faea4c5 | 2006-11-02 16:02:33 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 Tyan |
| 5 | * Copyright (C) 2006 AMD |
| 6 | * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. |
| 7 | * |
| 8 | * Copyright (C) 2006 MSI |
| 9 | * Written by bxshi <bingxunshi@gmail.com> for MSI. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 24 | */ |
| 25 | |
| 26 | #define ASSEMBLY 1 |
| 27 | #define __ROMCC__ |
| 28 | |
| 29 | #define RAMINIT_SYSINFO 1 |
| 30 | #define CACHE_AS_RAM_ADDRESS_DEBUG 0 |
| 31 | |
| 32 | #define SET_NB_CFG_54 1 |
| 33 | |
| 34 | //used by raminit |
| 35 | #define QRANK_DIMM_SUPPORT 1 |
| 36 | |
| 37 | //used by incoherent_ht |
| 38 | //#define K8_SCAN_PCI_BUS 1 |
| 39 | //#define K8_ALLOCATE_IO_RANGE 1 |
| 40 | |
| 41 | |
| 42 | //used by init_cpus and fidvid |
| 43 | #define K8_SET_FIDVID 1 |
| 44 | //if we want to wait for core1 done before DQS training, set it to 0 |
| 45 | #define K8_SET_FIDVID_CORE0_ONLY 1 |
| 46 | |
| 47 | #define DEBUG_SMBUS 1 |
| 48 | |
| 49 | #include <stdint.h> |
| 50 | #include <device/pci_def.h> |
| 51 | #include <device/pci_ids.h> |
| 52 | #include <arch/io.h> |
| 53 | #include <device/pnp_def.h> |
| 54 | #include <arch/romcc_io.h> |
| 55 | #include <cpu/x86/lapic.h> |
| 56 | #include "option_table.h" |
| 57 | #include "pc80/mc146818rtc_early.c" |
| 58 | #include "pc80/serial.c" |
| 59 | #include "arch/i386/lib/console.c" |
| 60 | |
| 61 | #if 0 |
| 62 | static void post_code(uint8_t value) { |
| 63 | #if 1 |
| 64 | int i; |
| 65 | for(i=0;i<0x80000;i++) { |
| 66 | outb(value, 0x80); |
| 67 | } |
| 68 | #endif |
| 69 | } |
| 70 | #endif |
| 71 | |
| 72 | #include <cpu/amd/model_fxx_rev.h> |
| 73 | #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" |
| 74 | #include "northbridge/amd/amdk8/raminit.h" |
| 75 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 76 | #include "lib/delay.c" |
| 77 | |
| 78 | #if CONFIG_USE_INIT == 0 |
| 79 | #include "lib/memcpy.c" |
| 80 | #endif |
| 81 | |
| 82 | |
| 83 | #include "cpu/x86/lapic/boot_cpu.c" |
| 84 | #include "northbridge/amd/amdk8/reset_test.c" |
| 85 | #include "northbridge/amd/amdk8/debug.c" |
| 86 | #include "superio/nsc/pc87417/pc87417_early_serial.c" |
| 87 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 88 | #include "cpu/x86/bist.h" |
| 89 | |
| 90 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 91 | |
| 92 | #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) |
| 93 | #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) |
| 94 | #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" |
| 95 | static void memreset_setup(void) |
| 96 | { |
| 97 | } |
| 98 | |
| 99 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 100 | { |
| 101 | } |
| 102 | |
| 103 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 104 | { |
| 105 | #define SMBUS_SWITCH1 0x70 |
| 106 | #define SMBUS_SWITCH2 0x72 |
| 107 | unsigned device = (ctrl->channel0[0]) >> 8; |
| 108 | smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); |
| 109 | smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); |
| 110 | } |
| 111 | |
| 112 | #if 0 |
| 113 | static inline void change_i2c_mux(unsigned device) |
| 114 | { |
| 115 | #define SMBUS_SWITCH1 0x70 |
| 116 | #define SMBUS_SWITCH2 0x72 |
| 117 | smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); |
| 118 | smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); |
| 119 | } |
| 120 | #endif |
| 121 | |
| 122 | |
| 123 | |
| 124 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 125 | { |
| 126 | return smbus_read_byte(device, address); |
| 127 | } |
| 128 | |
| 129 | #include "northbridge/amd/amdk8/amdk8_f.h" |
| 130 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 131 | |
| 132 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 133 | |
| 134 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 135 | |
| 136 | #include "sdram/generic_sdram.c" |
| 137 | |
| 138 | /* msi does not want the default */ |
| 139 | #include "resourcemap.c" |
| 140 | |
| 141 | #include "cpu/amd/dualcore/dualcore.c" |
| 142 | |
| 143 | #define RC0 (0x10<<8) |
| 144 | #define RC1 (0x01<<8) |
| 145 | |
| 146 | #define DIMM0 0x50 |
| 147 | #define DIMM1 0x51 |
| 148 | #define DIMM2 0x52 |
| 149 | #define DIMM3 0x53 |
| 150 | #define DIMM4 0x54 |
| 151 | #define DIMM5 0x55 |
| 152 | #define DIMM6 0x56 |
| 153 | #define DIMM7 0x57 |
| 154 | |
| 155 | |
| 156 | #include "cpu/amd/car/copy_and_run.c" |
| 157 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 158 | |
| 159 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 160 | |
| 161 | #include "cpu/amd/model_fxx/fidvid.c" |
| 162 | |
| 163 | #if USE_FALLBACK_IMAGE == 1 |
| 164 | |
| 165 | #include "northbridge/amd/amdk8/early_ht.c" |
| 166 | |
| 167 | void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) |
| 168 | { |
| 169 | |
| 170 | /* Is this a cpu only reset? Is this a secondary cpu? */ |
| 171 | if ((cpu_init_detectedx) || (!boot_cpu())) { |
| 172 | if (last_boot_normal()) { // RTC already inited |
| 173 | goto normal_image; |
| 174 | } else { |
| 175 | goto fallback_image; |
| 176 | } |
| 177 | } |
| 178 | /* Nothing special needs to be done to find bus 0 */ |
| 179 | /* Allow the HT devices to be found */ |
| 180 | |
| 181 | enumerate_ht_chain(); |
| 182 | |
| 183 | bcm5785_enable_rom(); |
| 184 | |
| 185 | bcm5785_enable_lpc(); |
| 186 | |
| 187 | //enable RTC |
| 188 | pc87417_enable_dev(RTC_DEV); |
| 189 | |
| 190 | /* Is this a deliberate reset by the bios */ |
| 191 | // post_code(0x22); |
| 192 | if (bios_reset_detected() && last_boot_normal()) { |
| 193 | goto normal_image; |
| 194 | } |
| 195 | /* This is the primary cpu how should I boot? */ |
| 196 | else if (do_normal_boot()) { |
| 197 | goto normal_image; |
| 198 | } |
| 199 | else { |
| 200 | goto fallback_image; |
| 201 | } |
| 202 | normal_image: |
| 203 | // post_code(0x23); |
| 204 | __asm__ volatile ("jmp __normal_image" |
| 205 | : /* outputs */ |
| 206 | : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ |
| 207 | ); |
| 208 | |
| 209 | fallback_image: |
| 210 | // post_code(0x25); |
| 211 | ; |
| 212 | |
| 213 | } |
| 214 | #endif |
| 215 | |
| 216 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx); |
| 217 | |
| 218 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 219 | { |
| 220 | |
| 221 | #if USE_FALLBACK_IMAGE == 1 |
| 222 | failover_process(bist, cpu_init_detectedx); |
| 223 | #endif |
| 224 | real_main(bist, cpu_init_detectedx); |
| 225 | |
| 226 | } |
| 227 | |
| 228 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 229 | { |
| 230 | static const uint16_t spd_addr[] = { |
| 231 | //first node |
| 232 | RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, |
| 233 | RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, |
| 234 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 235 | //second node |
| 236 | RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, |
| 237 | RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, |
| 238 | #endif |
| 239 | |
| 240 | }; |
| 241 | |
| 242 | struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); |
| 243 | |
| 244 | int needs_reset; |
| 245 | unsigned bsp_apicid = 0; |
| 246 | |
| 247 | if (bist == 0) { |
| 248 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 249 | } |
| 250 | |
| 251 | // post_code(0x32); |
| 252 | |
| 253 | pc87417_enable_serial(SERIAL_DEV, TTYS0_BASE); |
| 254 | uart_init(); |
| 255 | console_init(); |
| 256 | |
| 257 | // dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); |
| 258 | |
| 259 | /* Halt if there was a built in self test failure */ |
| 260 | report_bist_failure(bist); |
| 261 | |
| 262 | print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); |
| 263 | |
| 264 | setup_ms9185_resource_map(); |
| 265 | #if 0 |
| 266 | dump_pci_device(PCI_DEV(0, 0x18, 0)); |
| 267 | dump_pci_device(PCI_DEV(0, 0x19, 0)); |
| 268 | #endif |
| 269 | |
| 270 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); |
| 271 | |
| 272 | setup_coherent_ht_domain(); |
| 273 | |
| 274 | wait_all_core0_started(); |
| 275 | #if CONFIG_LOGICAL_CPUS==1 |
| 276 | // It is said that we should start core1 after all core0 launched |
| 277 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 278 | * So here need to make sure last core0 is started, esp for two way system, |
| 279 | * (there may be apic id conflicts in that case) |
| 280 | */ |
| 281 | start_other_cores(); |
| 282 | //bx_a010- wait_all_other_cores_started(bsp_apicid); |
| 283 | #endif |
| 284 | |
| 285 | /* it will set up chains and store link pair for optimization later */ |
| 286 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 287 | |
| 288 | bcm5785_early_setup(); |
| 289 | |
| 290 | |
| 291 | #if 0 |
| 292 | //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. |
| 293 | needs_reset = optimize_link_coherent_ht(); |
| 294 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 295 | #endif |
| 296 | |
| 297 | #if K8_SET_FIDVID == 1 |
| 298 | |
| 299 | { |
| 300 | msr_t msr; |
| 301 | msr=rdmsr(0xc0010042); |
| 302 | print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); |
| 303 | |
| 304 | } |
| 305 | |
| 306 | enable_fid_change(); |
| 307 | |
| 308 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 309 | |
| 310 | init_fidvid_bsp(bsp_apicid); |
| 311 | |
| 312 | // show final fid and vid |
| 313 | { |
| 314 | msr_t msr; |
| 315 | msr=rdmsr(0xc0010042); |
| 316 | print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); |
| 317 | |
| 318 | } |
| 319 | #endif |
| 320 | |
| 321 | #if 1 |
| 322 | needs_reset = optimize_link_coherent_ht(); |
| 323 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 324 | |
| 325 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 326 | if (needs_reset) { |
| 327 | print_info("ht reset -\r\n"); |
| 328 | soft_reset(); |
| 329 | } |
| 330 | #endif |
| 331 | allow_all_aps_stop(bsp_apicid); |
| 332 | |
| 333 | //It's the time to set ctrl in sysinfo now; |
| 334 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 335 | |
| 336 | enable_smbus(); |
| 337 | |
| 338 | #if 0 |
| 339 | int i; |
| 340 | for(i=0;i<2;i++) { |
| 341 | activate_spd_rom(sysinfo->ctrl+i); |
| 342 | dump_smbus_registers(); |
| 343 | } |
| 344 | #endif |
| 345 | |
| 346 | #if 0 |
| 347 | int i; |
| 348 | for(i=1;i<256;i<<=1) { |
| 349 | change_i2c_mux(i); |
| 350 | dump_smbus_registers(); |
| 351 | } |
| 352 | #endif |
| 353 | |
| 354 | memreset_setup(); |
| 355 | |
| 356 | //do we need apci timer, tsc...., only debug need it for better output |
| 357 | /* all ap stopped? */ |
| 358 | // init_timer(); // Need to use TMICT to synconize FID/VID |
| 359 | |
| 360 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 361 | |
| 362 | #if 0 |
| 363 | print_pci_devices(); |
| 364 | #endif |
| 365 | |
| 366 | #if 0 |
| 367 | // dump_pci_devices(); |
| 368 | dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); |
| 369 | dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); |
| 370 | #endif |
| 371 | |
| 372 | post_cache_as_ram(); |
| 373 | |
| 374 | |
| 375 | } |