Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 2 | |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 021c621 | 2021-01-26 11:28:47 +0200 | [diff] [blame] | 4 | #include <amdblocks/acpi.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 5 | #include <amdblocks/agesawrapper_call.h> |
Elyes Haouas | f743e0c | 2022-10-31 13:46:00 +0100 | [diff] [blame] | 6 | #include <amdblocks/agesawrapper.h> |
Michał Żygowski | 5a66202 | 2019-12-02 17:02:00 +0100 | [diff] [blame] | 7 | #include <amdblocks/biosram.h> |
Martin Roth | 8180427 | 2022-11-20 20:30:18 -0700 | [diff] [blame] | 8 | #include <amdblocks/post_codes.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 9 | #include <amdblocks/psp.h> |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 10 | #include <arch/romstage.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 11 | #include <cbmem.h> |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 12 | #include <commonlib/helpers.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 13 | #include <console/console.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 14 | #include <cpu/amd/mtrr.h> |
Elyes Haouas | f743e0c | 2022-10-31 13:46:00 +0100 | [diff] [blame] | 15 | #include <cpu/cpu.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 16 | #include <cpu/x86/msr.h> |
| 17 | #include <cpu/x86/mtrr.h> |
| 18 | #include <cpu/x86/smm.h> |
Marshall Dawson | 3e4e4c5 | 2017-11-10 16:08:37 -0700 | [diff] [blame] | 19 | #include <device/device.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Daniel Kurtz | c6c8972 | 2018-05-24 17:57:37 -0600 | [diff] [blame] | 21 | #include <elog.h> |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 22 | #include <program_loading.h> |
| 23 | #include <romstage_common.h> |
| 24 | #include <romstage_handoff.h> |
Felix Held | 4892d73 | 2023-03-03 16:08:57 +0100 | [diff] [blame] | 25 | #include <soc/iomap.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 26 | #include <soc/northbridge.h> |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 27 | #include <soc/pci_devs.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 28 | #include <soc/southbridge.h> |
Arthur Heymans | 796147f | 2022-02-15 10:59:41 +0100 | [diff] [blame] | 29 | #include <stdint.h> |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 30 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 31 | #include "chip.h" |
| 32 | |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 33 | void __weak mainboard_romstage_entry(void) |
Martin Roth | 2c3e3ef | 2018-04-11 16:35:08 -0600 | [diff] [blame] | 34 | { |
| 35 | /* By default, don't do anything */ |
| 36 | } |
| 37 | |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 38 | static void agesa_call(void) |
| 39 | { |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 40 | post_code(POSTCODE_AGESA_AMDINITRESET); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 41 | do_agesawrapper(AMD_INIT_RESET, "amdinitreset"); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 42 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 43 | post_code(POSTCODE_AGESA_AMDINITEARLY); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 44 | /* APs will not exit amdinitearly */ |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 45 | do_agesawrapper(AMD_INIT_EARLY, "amdinitearly"); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 46 | } |
| 47 | |
| 48 | static void bsp_agesa_call(void) |
| 49 | { |
| 50 | set_ap_entry_ptr(agesa_call); /* indicate the path to the AP */ |
| 51 | agesa_call(); |
| 52 | } |
Arthur Heymans | bab9e2e | 2021-05-29 07:30:33 +0200 | [diff] [blame] | 53 | void __noreturn romstage_main(void) |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 54 | { |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 55 | msr_t base, mask; |
| 56 | msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); |
| 57 | int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 58 | int s3_resume = acpi_is_wakeup_s3(); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 59 | int i; |
| 60 | |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 61 | soc_enable_psp_early(); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 62 | if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW)) |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 63 | psp_load_named_blob(BLOB_SMU_FW, "smu_fw"); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 64 | |
Kyösti Mälkki | 9e591c4 | 2021-01-09 12:37:25 +0200 | [diff] [blame] | 65 | mainboard_romstage_entry(); |
Kyösti Mälkki | 7f50afb | 2019-09-11 17:12:26 +0300 | [diff] [blame] | 66 | elog_boot_notify(s3_resume); |
Raul E Rangel | 873b4e7 | 2018-06-12 10:53:55 -0600 | [diff] [blame] | 67 | |
| 68 | bsp_agesa_call(); |
| 69 | |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 70 | if (!s3_resume) { |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 71 | post_code(POSTCODE_AGESA_AMDINITPOST); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 72 | do_agesawrapper(AMD_INIT_POST, "amdinitpost"); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 73 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 74 | post_code(POSTCODE_AGESA_AMDINITPOST_DONE); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 75 | /* |
| 76 | * TODO: This is a hack to work around current AGESA behavior. |
| 77 | * AGESA needs to change to reflect that coreboot owns |
| 78 | * the MTRRs. |
| 79 | * |
| 80 | * After setting up DRAM, AGESA also completes the configuration |
| 81 | * of the MTRRs, setting regions to WB. Anything written to |
Elyes HAOUAS | ba4dbf8 | 2021-01-16 15:02:17 +0100 | [diff] [blame] | 82 | * memory between now and when CAR is dismantled will be |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 83 | * in cache and lost. For now, set the regions UC to ensure |
| 84 | * the writes get to DRAM. |
| 85 | */ |
| 86 | for (i = 0 ; i < vmtrrs ; i++) { |
| 87 | base = rdmsr(MTRR_PHYS_BASE(i)); |
| 88 | mask = rdmsr(MTRR_PHYS_MASK(i)); |
| 89 | if (!(mask.lo & MTRR_PHYS_MASK_VALID)) |
| 90 | continue; |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 91 | |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 92 | if ((base.lo & 0x7) == MTRR_TYPE_WRBACK) { |
| 93 | base.lo &= ~0x7; |
| 94 | base.lo |= MTRR_TYPE_UNCACHEABLE; |
| 95 | wrmsr(MTRR_PHYS_BASE(i), base); |
| 96 | } |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 97 | } |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 98 | /* Disable WB from to region 4GB-TOM2. */ |
| 99 | msr_t sys_cfg = rdmsr(SYSCFG_MSR); |
| 100 | sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; |
| 101 | wrmsr(SYSCFG_MSR, sys_cfg); |
| 102 | } else { |
| 103 | printk(BIOS_INFO, "S3 detected\n"); |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 104 | post_code(POSTCODE_AGESA_AMDINITRESUME); |
Kyösti Mälkki | 6e512c4 | 2018-06-14 06:57:05 +0300 | [diff] [blame] | 105 | do_agesawrapper(AMD_INIT_RESUME, "amdinitresume"); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 106 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 107 | post_code(POSTCODE_AGESA_AMDINITRESUME_DONE); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 108 | } |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 109 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 110 | post_code(POSTCODE_PSP_NOTIFY_DRAM); |
Marshall Dawson | a7bfbbe | 2017-09-13 17:24:53 -0600 | [diff] [blame] | 111 | psp_notify_dram(); |
| 112 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 113 | post_code(POSTCODE_PSP_NOTIFY_DRAM_DONE); |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 114 | if (cbmem_recovery(s3_resume)) |
| 115 | printk(BIOS_CRIT, "Failed to recover cbmem\n"); |
| 116 | if (romstage_handoff_init(s3_resume)) |
| 117 | printk(BIOS_ERR, "Failed to set romstage handoff data\n"); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 118 | |
Kyösti Mälkki | 7cdb047 | 2019-08-08 11:16:06 +0300 | [diff] [blame] | 119 | if (CONFIG(SMM_TSEG)) |
| 120 | smm_list_regions(); |
| 121 | |
Yuchen He | 1e67adb | 2023-07-25 21:28:36 +0200 | [diff] [blame^] | 122 | post_code(POSTCODE_ROMSTAGE_RUN_POSTCAR); |
Arthur Heymans | 876a1b4 | 2022-02-15 11:06:10 +0100 | [diff] [blame] | 123 | prepare_and_run_postcar(); |
Arthur Heymans | 796147f | 2022-02-15 10:59:41 +0100 | [diff] [blame] | 124 | } |
Marshall Dawson | 18b477e | 2017-09-21 12:27:12 -0600 | [diff] [blame] | 125 | |
Arthur Heymans | 796147f | 2022-02-15 10:59:41 +0100 | [diff] [blame] | 126 | void fill_postcar_frame(struct postcar_frame *pcf) |
| 127 | { |
| 128 | uintptr_t top_of_ram = (uintptr_t)cbmem_top(); |
| 129 | postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 130 | |
Subrata Banik | 3eff037 | 2019-09-10 15:51:17 +0530 | [diff] [blame] | 131 | /* Cache the TSEG region */ |
Arthur Heymans | 796147f | 2022-02-15 10:59:41 +0100 | [diff] [blame] | 132 | postcar_enable_tseg_cache(pcf); |
Marshall Dawson | 9df969a | 2017-07-25 18:46:46 -0600 | [diff] [blame] | 133 | } |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 134 | |
| 135 | void SetMemParams(AMD_POST_PARAMS *PostParams) |
| 136 | { |
| 137 | const struct soc_amd_stoneyridge_config *cfg; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 138 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 139 | |
| 140 | if (!dev || !dev->chip_info) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 141 | printk(BIOS_ERR, "Cannot find SoC devicetree config\n"); |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 142 | /* In case of a BIOS error, only attempt to set UMA. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 143 | PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 144 | UMA_AUTO : UMA_NONE; |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 145 | return; |
| 146 | } |
| 147 | |
| 148 | cfg = dev->chip_info; |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 149 | |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 150 | PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; |
Aaron Durbin | 36dbf1d | 2017-11-10 13:16:23 -0700 | [diff] [blame] | 151 | |
| 152 | switch (cfg->uma_mode) { |
| 153 | case UMAMODE_NONE: |
| 154 | PostParams->MemConfig.UmaMode = UMA_NONE; |
| 155 | break; |
| 156 | case UMAMODE_SPECIFIED_SIZE: |
| 157 | PostParams->MemConfig.UmaMode = UMA_SPECIFIED; |
| 158 | /* 64 KiB blocks. */ |
| 159 | PostParams->MemConfig.UmaSize = cfg->uma_size / (64 * KiB); |
| 160 | break; |
| 161 | case UMAMODE_AUTO_LEGACY: |
| 162 | PostParams->MemConfig.UmaMode = UMA_AUTO; |
| 163 | PostParams->MemConfig.UmaVersion = UMA_LEGACY; |
| 164 | break; |
| 165 | case UMAMODE_AUTO_NON_LEGACY: |
| 166 | PostParams->MemConfig.UmaMode = UMA_AUTO; |
| 167 | PostParams->MemConfig.UmaVersion = UMA_NON_LEGACY; |
| 168 | break; |
| 169 | } |
Richard Spiegel | 67c2a7b | 2017-11-09 16:04:35 -0700 | [diff] [blame] | 170 | } |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 171 | |
| 172 | void soc_customize_init_early(AMD_EARLY_PARAMS *InitEarly) |
| 173 | { |
| 174 | const struct soc_amd_stoneyridge_config *cfg; |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 175 | const struct device *dev = pcidev_path_on_root(GNB_DEVFN); |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 176 | struct _PLATFORM_CONFIGURATION *platform; |
| 177 | |
| 178 | if (!dev || !dev->chip_info) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 179 | printk(BIOS_WARNING, "Cannot find SoC devicetree" |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 180 | " config, STAPM unchanged\n"); |
| 181 | return; |
| 182 | } |
| 183 | cfg = dev->chip_info; |
| 184 | platform = &InitEarly->PlatformConfig; |
Richard Spiegel | de5d040 | 2018-10-11 08:15:43 -0700 | [diff] [blame] | 185 | if ((cfg->stapm_percent) && (cfg->stapm_time_ms) && |
| 186 | (cfg->stapm_power_mw)) { |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 187 | platform->PlatStapmConfig.CfgStapmScalar = cfg->stapm_percent; |
| 188 | platform->PlatStapmConfig.CfgStapmTimeConstant = |
Richard Spiegel | de5d040 | 2018-10-11 08:15:43 -0700 | [diff] [blame] | 189 | cfg->stapm_time_ms; |
| 190 | platform->PkgPwrLimitDC = cfg->stapm_power_mw; |
| 191 | platform->PkgPwrLimitAC = cfg->stapm_power_mw; |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 192 | platform->PlatStapmConfig.CfgStapmBoost = StapmBoostEnabled; |
| 193 | } |
Felix Held | 4892d73 | 2023-03-03 16:08:57 +0100 | [diff] [blame] | 194 | |
| 195 | /* Make binaryPi use ACPI_CSTATE_CONTROL as C state control IO range. It gets written |
| 196 | into MSR_CSTATE_ADDRESS and used in the _CST packages in the PSTATE SSDT. */ |
| 197 | platform->CStateIoBaseAddress = ACPI_CSTATE_CONTROL; |
Richard Spiegel | dd9b1d1 | 2018-09-20 14:50:11 -0700 | [diff] [blame] | 198 | } |
Kyösti Mälkki | 021c621 | 2021-01-26 11:28:47 +0200 | [diff] [blame] | 199 | |
| 200 | static void migrate_power_state(int is_recovery) |
| 201 | { |
| 202 | struct chipset_power_state *state; |
| 203 | state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); |
| 204 | if (state) { |
| 205 | acpi_fill_pm_gpe_state(&state->gpe_state); |
| 206 | acpi_pm_gpe_add_events_print_events(); |
| 207 | } |
Kyösti Mälkki | 021c621 | 2021-01-26 11:28:47 +0200 | [diff] [blame] | 208 | } |
Kyösti Mälkki | fa3bc04 | 2022-03-31 07:40:10 +0300 | [diff] [blame] | 209 | CBMEM_CREATION_HOOK(migrate_power_state); |