Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 1 | config SOC_INTEL_CANNONLAKE_BASE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 2 | bool |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 3 | |
Arthur Heymans | 4821a0e | 2019-06-18 13:19:29 +0200 | [diff] [blame] | 4 | config SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 5 | bool |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 6 | default y if SOC_INTEL_CANNONLAKE_BASE && !SOC_INTEL_CANNONLAKE |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 7 | help |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 8 | Single Kconfig option to select common base Cannonlake support. |
| 9 | This Kconfig will help to select majority of CNL SoC features. |
| 10 | Major difference that exist today between |
Arthur Heymans | 4821a0e | 2019-06-18 13:19:29 +0200 | [diff] [blame] | 11 | SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS and SOC_INTEL_CANNONLAKE Kconfig |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 12 | are in FSP Header Files. Hence this Kconfig might help to select |
| 13 | required SoC support FSP headers. Any future Intel SoC would |
| 14 | like to make use of CNL support might just select this Kconfig. |
| 15 | |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 16 | config SOC_INTEL_CANNONLAKE |
| 17 | bool |
| 18 | select SOC_INTEL_CANNONLAKE_BASE |
Arthur Heymans | a449290 | 2019-06-17 10:50:47 +0200 | [diff] [blame] | 19 | select MICROCODE_BLOB_NOT_IN_BLOB_REPO |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 20 | help |
| 21 | Intel Cannonlake support |
| 22 | |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 23 | config SOC_INTEL_COFFEELAKE |
| 24 | bool |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 25 | select SOC_INTEL_CANNONLAKE_BASE |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 26 | help |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 27 | Intel Coffeelake support |
| 28 | |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 29 | config SOC_INTEL_WHISKEYLAKE |
| 30 | bool |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 31 | select SOC_INTEL_CANNONLAKE_BASE |
Bora Guvendik | 349b6a1 | 2019-06-24 14:33:31 -0700 | [diff] [blame] | 32 | select FSP_USES_CB_STACK |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 33 | help |
| 34 | Intel Whiskeylake support |
| 35 | |
Subrata Banik | fa011db | 2019-02-02 13:25:14 +0530 | [diff] [blame] | 36 | config SOC_INTEL_COMETLAKE |
| 37 | bool |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 38 | select SOC_INTEL_CANNONLAKE_BASE |
Arthur Heymans | a449290 | 2019-06-17 10:50:47 +0200 | [diff] [blame] | 39 | select MICROCODE_BLOB_UNDISCLOSED |
Aamir Bohra | f2ad8b3 | 2019-07-08 12:22:28 +0530 | [diff] [blame] | 40 | select FSP_USES_CB_STACK |
Subrata Banik | fa011db | 2019-02-02 13:25:14 +0530 | [diff] [blame] | 41 | help |
| 42 | Intel Cometlake support |
| 43 | |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 44 | config SOC_INTEL_CANNONLAKE_PCH_H |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 45 | bool |
Lijian Zhao | 3638a52 | 2018-07-12 17:16:11 -0700 | [diff] [blame] | 46 | help |
| 47 | Choose this option if you have a PCH-H chipset. |
| 48 | |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 49 | if SOC_INTEL_CANNONLAKE_BASE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 50 | |
| 51 | config CPU_SPECIFIC_OPTIONS |
| 52 | def_bool y |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 53 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 54 | select ACPI_NHLT |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 55 | select ARCH_BOOTBLOCK_X86_32 |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 56 | select ARCH_RAMSTAGE_X86_32 |
| 57 | select ARCH_ROMSTAGE_X86_32 |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 58 | select ARCH_VERSTAGE_X86_32 |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 59 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 60 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 61 | select C_ENVIRONMENT_BOOTBLOCK |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 62 | select CACHE_MRC_SETTINGS |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 63 | select COMMON_FADT |
Ronak Kanabar | a432f38 | 2019-03-16 21:26:43 +0530 | [diff] [blame] | 64 | select CPU_INTEL_COMMON |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 65 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Furquan Shaikh | cef9879 | 2019-04-10 16:31:55 -0700 | [diff] [blame] | 66 | select FSP_M_XIP |
Nick Vaccaro | 69b5cdb | 2017-08-29 19:25:23 -0700 | [diff] [blame] | 67 | select GENERIC_GPIO_LIB |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 68 | select HAVE_FSP_GOP |
Stefan Tauner | ef8b957 | 2018-09-06 00:34:28 +0200 | [diff] [blame] | 69 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 70 | select HAVE_SMI_HANDLER |
Aamir Bohra | e462585 | 2018-05-29 10:52:33 +0530 | [diff] [blame] | 71 | select IDT_IN_EVERY_STAGE |
Abhay Kumar | b0c4cbb | 2017-10-12 11:33:01 -0700 | [diff] [blame] | 72 | select INTEL_GMA_ACPI |
Nico Huber | 29cc331 | 2018-06-06 17:40:02 +0200 | [diff] [blame] | 73 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Lijian Zhao | a515849 | 2017-08-29 14:37:17 -0700 | [diff] [blame] | 74 | select IOAPIC |
Lijian Zhao | a06f55b | 2017-10-04 23:08:55 -0700 | [diff] [blame] | 75 | select MRC_SETTINGS_PROTECT |
Furquan Shaikh | 09b01de | 2019-04-09 16:26:29 -0700 | [diff] [blame] | 76 | select NO_FIXED_XIP_ROM_SIZE |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 77 | select PARALLEL_MP |
| 78 | select PARALLEL_MP_AP_WORK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 79 | select PLATFORM_USES_FSP2_0 |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 80 | select REG_SCRIPT |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 81 | select SMP |
Subrata Banik | ac1cd44 | 2018-02-06 15:25:27 +0530 | [diff] [blame] | 82 | select SOC_AHCI_PORT_IMPLEMENTED_INVERT |
Julien Viard de Galbert | 2912e8e | 2018-08-14 16:15:26 +0200 | [diff] [blame] | 83 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 84 | select SOC_INTEL_COMMON |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 85 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 86 | select SOC_INTEL_COMMON_BLOCK |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 87 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 88 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 89 | select SOC_INTEL_COMMON_BLOCK_CPU |
Pratik Prajapati | 01eda28 | 2017-08-17 21:09:45 -0700 | [diff] [blame] | 90 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Tim Wawrzynczak | 939440c | 2019-04-26 15:03:33 -0600 | [diff] [blame] | 91 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Furquan Shaikh | a5bb716 | 2017-12-20 11:09:04 -0800 | [diff] [blame] | 92 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
praveen hodagatta pranesh | dc4fceb | 2018-10-16 18:06:18 +0800 | [diff] [blame] | 93 | select SOC_INTEL_COMMON_BLOCK_HDA |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 94 | select SOC_INTEL_COMMON_BLOCK_SA |
Paul Fagerburg | 7803e48 | 2019-06-27 10:44:51 -0600 | [diff] [blame] | 95 | select SOC_INTEL_COMMON_BLOCK_XHCI |
| 96 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Brandon Breitenstein | ae15486 | 2017-08-01 11:32:06 -0700 | [diff] [blame] | 97 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 98 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | f513ceb | 2018-05-17 15:57:43 +0530 | [diff] [blame] | 99 | select SOC_INTEL_COMMON_PCH_BASE |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 100 | select SOC_INTEL_COMMON_NHLT |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 101 | select SOC_INTEL_COMMON_RESET |
Lijian Zhao | f0eb999 | 2017-09-14 14:51:12 -0700 | [diff] [blame] | 102 | select SSE2 |
Lijian Zhao | acfc149 | 2017-07-06 15:27:27 -0700 | [diff] [blame] | 103 | select SUPPORT_CPU_UCODE_IN_CBFS |
Lijian Zhao | dcf99b0 | 2017-07-30 15:40:10 -0700 | [diff] [blame] | 104 | select TSC_CONSTANT_RATE |
| 105 | select TSC_MONOTONIC_TIMER |
| 106 | select UDELAY_TSC |
Subrata Banik | 7455881 | 2018-01-25 11:41:04 +0530 | [diff] [blame] | 107 | select UDK_2017_BINDING |
Subrata Banik | a8733e3 | 2018-01-23 16:40:56 +0530 | [diff] [blame] | 108 | select DISPLAY_FSP_VERSION_INFO |
Praveen hodagatta pranesh | b66757f | 2018-10-23 02:43:05 +0800 | [diff] [blame] | 109 | select FSP_T_XIP if FSP_CAR |
Subrata Banik | a0368a0 | 2019-06-04 14:16:02 +0530 | [diff] [blame] | 110 | select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 111 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 112 | config DCACHE_RAM_BASE |
| 113 | default 0xfef00000 |
| 114 | |
| 115 | config DCACHE_RAM_SIZE |
| 116 | default 0x40000 |
| 117 | help |
| 118 | The size of the cache-as-ram region required during bootblock |
| 119 | and/or romstage. |
| 120 | |
| 121 | config DCACHE_BSP_STACK_SIZE |
| 122 | hex |
Aamir Bohra | f2ad8b3 | 2019-07-08 12:22:28 +0530 | [diff] [blame] | 123 | default 0x20000 if FSP_USES_CB_STACK |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 124 | default 0x4000 |
| 125 | help |
| 126 | The amount of anticipated stack usage in CAR by bootblock and |
| 127 | other stages. |
| 128 | |
Subrata Banik | 1d260e6 | 2019-09-09 13:55:42 +0530 | [diff] [blame] | 129 | config FSP_TEMP_RAM_SIZE |
| 130 | hex |
| 131 | depends on FSP_USES_CB_STACK |
| 132 | default 0x10000 |
| 133 | help |
| 134 | The amount of anticipated heap usage in CAR by FSP. |
| 135 | Refer to Platform FSP integration guide document to know |
| 136 | the exact FSP requirement for Heap setup. |
| 137 | |
Furquan Shaikh | c0257dd | 2018-05-02 23:29:04 -0700 | [diff] [blame] | 138 | config IFD_CHIPSET |
| 139 | string |
| 140 | default "cnl" |
| 141 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 142 | config IED_REGION_SIZE |
| 143 | hex |
| 144 | default 0x400000 |
| 145 | |
John Zhao | 7492bcb | 2018-02-01 15:56:28 -0800 | [diff] [blame] | 146 | config HEAP_SIZE |
| 147 | hex |
| 148 | default 0x8000 |
| 149 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 150 | config NHLT_DMIC_1CH_16B |
| 151 | bool |
| 152 | depends on ACPI_NHLT |
| 153 | default n |
| 154 | help |
| 155 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 156 | |
| 157 | config NHLT_DMIC_2CH_16B |
| 158 | bool |
| 159 | depends on ACPI_NHLT |
| 160 | default n |
| 161 | help |
| 162 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 163 | |
| 164 | config NHLT_DMIC_4CH_16B |
| 165 | bool |
| 166 | depends on ACPI_NHLT |
| 167 | default n |
| 168 | help |
| 169 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 170 | |
| 171 | config NHLT_MAX98357 |
| 172 | bool |
| 173 | depends on ACPI_NHLT |
| 174 | default n |
| 175 | help |
| 176 | Include DSP firmware settings for headset codec. |
| 177 | |
N, Harshapriya | 4a1ee4b | 2017-11-28 14:29:26 -0800 | [diff] [blame] | 178 | config NHLT_MAX98373 |
| 179 | bool |
| 180 | depends on ACPI_NHLT |
| 181 | default n |
| 182 | help |
| 183 | Include DSP firmware settings for headset codec. |
| 184 | |
Lijian Zhao | 0e956f2 | 2017-10-22 18:30:39 -0700 | [diff] [blame] | 185 | config NHLT_DA7219 |
| 186 | bool |
| 187 | depends on ACPI_NHLT |
| 188 | default n |
| 189 | help |
| 190 | Include DSP firmware settings for headset codec. |
| 191 | |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 192 | config MAX_ROOT_PORTS |
| 193 | int |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 194 | default 24 if SOC_INTEL_CANNONLAKE_PCH_H |
Lijian Zhao | c85890d | 2017-10-20 09:19:07 -0700 | [diff] [blame] | 195 | default 16 |
Pratik Prajapati | c8c741d | 2017-08-29 11:38:42 -0700 | [diff] [blame] | 196 | |
Lijian Zhao | d5d89c8 | 2019-05-07 14:05:33 -0700 | [diff] [blame] | 197 | config MAX_PCIE_CLOCKS |
| 198 | int |
| 199 | default 16 if SOC_INTEL_CANNONLAKE_PCH_H |
| 200 | default 6 |
| 201 | |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 202 | config SMM_TSEG_SIZE |
| 203 | hex |
| 204 | default 0x800000 |
| 205 | |
Subrata Banik | e66600e | 2018-05-10 17:23:56 +0530 | [diff] [blame] | 206 | config SMM_RESERVED_SIZE |
| 207 | hex |
| 208 | default 0x200000 |
| 209 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 210 | config PCR_BASE_ADDRESS |
| 211 | hex |
| 212 | default 0xfd000000 |
| 213 | help |
| 214 | This option allows you to select MMIO Base Address of sideband bus. |
| 215 | |
Andrey Petrov | 3e2e050 | 2017-06-05 13:22:24 -0700 | [diff] [blame] | 216 | config CPU_BCLK_MHZ |
| 217 | int |
| 218 | default 100 |
| 219 | |
Aaron Durbin | 551e4be | 2018-04-10 09:24:54 -0600 | [diff] [blame] | 220 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
Lijian Zhao | f388561 | 2017-11-09 15:01:33 -0800 | [diff] [blame] | 221 | int |
| 222 | default 120 |
| 223 | |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 224 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 225 | int |
Duncan Laurie | 695f2fe | 2018-12-05 12:51:23 -0800 | [diff] [blame] | 226 | default 216 |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 227 | |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 228 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 229 | int |
| 230 | default 3 |
| 231 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 232 | config SOC_INTEL_I2C_DEV_MAX |
| 233 | int |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 234 | default 4 if SOC_INTEL_CANNONLAKE_PCH_H |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 235 | default 6 |
| 236 | |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 237 | config CONSOLE_UART_BASE_ADDRESS |
| 238 | hex |
| 239 | default 0xfe032000 |
| 240 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 241 | |
Lijian Zhao | 8465a81 | 2017-07-11 12:33:22 -0700 | [diff] [blame] | 242 | # Clock divider parameters for 115200 baud rate |
| 243 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 244 | hex |
| 245 | default 0x30 |
| 246 | |
| 247 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 248 | hex |
| 249 | default 0xc35 |
| 250 | |
Lijian Zhao | 6d7063c | 2017-08-29 17:26:48 -0700 | [diff] [blame] | 251 | config CHROMEOS |
| 252 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 253 | |
| 254 | config VBOOT |
| 255 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 256 | select VBOOT_MUST_REQUEST_DISPLAY |
Lijian Zhao | 6d7063c | 2017-08-29 17:26:48 -0700 | [diff] [blame] | 257 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
| 258 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 259 | select VBOOT_VBNV_CMOS |
| 260 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 261 | |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 262 | config C_ENV_BOOTBLOCK_SIZE |
| 263 | hex |
Duncan Laurie | 11340e5 | 2018-12-01 16:58:52 -0800 | [diff] [blame] | 264 | default 0xC000 |
Aaron Durbin | 4a8f45f | 2017-10-05 17:05:36 -0600 | [diff] [blame] | 265 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 266 | config CBFS_SIZE |
| 267 | hex |
| 268 | default 0x200000 |
| 269 | |
Rizwan Qureshi | 8aadab7 | 2019-02-17 11:31:21 +0530 | [diff] [blame] | 270 | config MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE |
| 271 | bool |
| 272 | default n |
| 273 | help |
| 274 | Select this if the board has a SD_PWR_ENABLE pin connected to a |
| 275 | active high sensing load switch to turn on power to the card reader. |
| 276 | This will enable a workaround in ASL _PS3 and _PS0 methods to force |
| 277 | SD_PWR_ENABLE to stay low in D3. |
| 278 | |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 279 | choice |
| 280 | prompt "Cache-as-ram implementation" |
Angel Pons | 7ed704d | 2019-07-12 15:46:43 +0200 | [diff] [blame] | 281 | default USE_CANNONLAKE_CAR_NEM_ENHANCED |
Subrata Banik | 9e3ba21 | 2018-01-08 15:28:26 +0530 | [diff] [blame] | 282 | help |
| 283 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 284 | |
| 285 | config USE_CANNONLAKE_CAR_NEM_ENHANCED |
| 286 | bool "Enhanced Non-evict mode" |
| 287 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 288 | select INTEL_CAR_NEM_ENHANCED |
| 289 | help |
| 290 | A current limitation of NEM (Non-Evict mode) is that code and data |
| 291 | sizes are derived from the requirement to not write out any modified |
| 292 | cache line. With NEM, if there is no physical memory behind the |
| 293 | cached area, the modified data will be lost and NEM results will be |
| 294 | inconsistent. ENHANCED NEM guarantees that modified data is always |
| 295 | kept in cache while clean data is replaced. |
| 296 | |
| 297 | config USE_CANNONLAKE_FSP_CAR |
| 298 | bool "Use FSP CAR" |
| 299 | select FSP_CAR |
| 300 | help |
| 301 | Use FSP APIs to initialize and tear down the Cache-As-Ram. |
| 302 | |
| 303 | endchoice |
| 304 | |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 305 | config FSP_HEADER_PATH |
Patrick Georgi | c6382cd | 2018-10-26 22:03:17 +0200 | [diff] [blame] | 306 | string "Location of FSP headers" |
Subrata Banik | 6527b1a | 2019-01-29 11:04:25 +0530 | [diff] [blame] | 307 | default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE |
Subrata Banik | fa011db | 2019-02-02 13:25:14 +0530 | [diff] [blame] | 308 | default "src/vendorcode/intel/fsp/fsp2_0/cometlake/" if SOC_INTEL_COMETLAKE |
Arthur Heymans | c8db633 | 2019-06-17 13:32:13 +0200 | [diff] [blame] | 309 | default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if SOC_INTEL_CANNONLAKE |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 310 | |
| 311 | config FSP_FD_PATH |
| 312 | string |
| 313 | depends on FSP_USE_REPO |
Matt DeVillier | 73b0136 | 2019-04-23 12:03:03 -0500 | [diff] [blame] | 314 | default "3rdparty/fsp/CoffeeLakeFspBinPkg/FSP.fd" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE |
Patrick Georgi | 6539e10 | 2018-09-13 11:48:43 -0400 | [diff] [blame] | 315 | |
Kane Chen | 3717256 | 2019-04-11 21:55:20 +0800 | [diff] [blame] | 316 | config SOC_INTEL_CANNONLAKE_DEBUG_CONSENT |
| 317 | int "Debug Consent for CNL" |
| 318 | # USB DBC is more common for developers so make this default to 3 if |
| 319 | # SOC_INTEL_DEBUG_CONSENT=y |
| 320 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 321 | default 0 |
| 322 | help |
| 323 | This is to control debug interface on SOC. |
| 324 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 325 | PlatformDebugConsent in FspmUpd.h has the details. |
| 326 | |
Subrata Banik | 5ee4c12 | 2019-07-05 06:43:46 +0530 | [diff] [blame] | 327 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 328 | hex |
| 329 | default 0xe00 |
| 330 | |
Patrick Rudolph | 5fffb5e | 2019-07-25 11:55:30 +0200 | [diff] [blame] | 331 | config INTEL_TXT_BIOSACM_ALIGNMENT |
| 332 | hex |
| 333 | default 0x40000 # 256KB |
| 334 | |
Lijian Zhao | 8109604 | 2017-05-02 18:54:44 -0700 | [diff] [blame] | 335 | endif |