Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 4 | #include <acpi/acpi_gnvs.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpigen.h> |
Arthur Heymans | d90154c | 2022-12-02 13:27:35 +0100 | [diff] [blame] | 6 | #include <arch/ioapic.h> |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 7 | #include <arch/smp/mpspec.h> |
Patrick Georgi | 39c3d39 | 2019-04-23 12:27:22 +0200 | [diff] [blame] | 8 | #include <console/console.h> |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 9 | #include <device/mmio.h> |
| 10 | #include <device/pci_ops.h> |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 11 | #include <intelblocks/cpulib.h> |
| 12 | #include <intelblocks/pmclib.h> |
| 13 | #include <intelblocks/acpi.h> |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 14 | #include <intelblocks/p2sb.h> |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 15 | #include <soc/cpu.h> |
| 16 | #include <soc/iomap.h> |
| 17 | #include <soc/nvs.h> |
| 18 | #include <soc/pci_devs.h> |
| 19 | #include <soc/pm.h> |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 20 | #include <soc/systemagent.h> |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 21 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 22 | #include "chip.h" |
| 23 | |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 24 | /* |
| 25 | * List of supported C-states in this processor. |
| 26 | */ |
| 27 | enum { |
| 28 | C_STATE_C0, /* 0 */ |
| 29 | C_STATE_C1, /* 1 */ |
| 30 | C_STATE_C1E, /* 2 */ |
| 31 | C_STATE_C6_SHORT_LAT, /* 3 */ |
| 32 | C_STATE_C6_LONG_LAT, /* 4 */ |
| 33 | C_STATE_C7_SHORT_LAT, /* 5 */ |
| 34 | C_STATE_C7_LONG_LAT, /* 6 */ |
| 35 | C_STATE_C7S_SHORT_LAT, /* 7 */ |
| 36 | C_STATE_C7S_LONG_LAT, /* 8 */ |
| 37 | C_STATE_C8, /* 9 */ |
| 38 | C_STATE_C9, /* 10 */ |
| 39 | C_STATE_C10, /* 11 */ |
| 40 | NUM_C_STATES |
| 41 | }; |
| 42 | |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 43 | static const acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 44 | [C_STATE_C0] = {}, |
| 45 | [C_STATE_C1] = { |
| 46 | .latency = 0, |
| 47 | .power = C1_POWER, |
| 48 | .resource = MWAIT_RES(0, 0), |
| 49 | }, |
| 50 | [C_STATE_C1E] = { |
| 51 | .latency = 0, |
| 52 | .power = C1_POWER, |
| 53 | .resource = MWAIT_RES(0, 1), |
| 54 | }, |
| 55 | [C_STATE_C6_SHORT_LAT] = { |
Nico Huber | 792ed63 | 2021-07-26 13:44:19 +0000 | [diff] [blame] | 56 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 57 | .power = C6_POWER, |
| 58 | .resource = MWAIT_RES(2, 0), |
| 59 | }, |
| 60 | [C_STATE_C6_LONG_LAT] = { |
Nico Huber | 792ed63 | 2021-07-26 13:44:19 +0000 | [diff] [blame] | 61 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 62 | .power = C6_POWER, |
| 63 | .resource = MWAIT_RES(2, 1), |
| 64 | }, |
| 65 | [C_STATE_C7_SHORT_LAT] = { |
Nico Huber | 792ed63 | 2021-07-26 13:44:19 +0000 | [diff] [blame] | 66 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 67 | .power = C7_POWER, |
| 68 | .resource = MWAIT_RES(3, 0), |
| 69 | }, |
| 70 | [C_STATE_C7_LONG_LAT] = { |
Nico Huber | 792ed63 | 2021-07-26 13:44:19 +0000 | [diff] [blame] | 71 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 72 | .power = C7_POWER, |
| 73 | .resource = MWAIT_RES(3, 1), |
| 74 | }, |
| 75 | [C_STATE_C7S_SHORT_LAT] = { |
Nico Huber | 792ed63 | 2021-07-26 13:44:19 +0000 | [diff] [blame] | 76 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 77 | .power = C7_POWER, |
| 78 | .resource = MWAIT_RES(3, 2), |
| 79 | }, |
| 80 | [C_STATE_C7S_LONG_LAT] = { |
Nico Huber | 792ed63 | 2021-07-26 13:44:19 +0000 | [diff] [blame] | 81 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 82 | .power = C7_POWER, |
| 83 | .resource = MWAIT_RES(3, 3), |
| 84 | }, |
| 85 | [C_STATE_C8] = { |
Nico Huber | 792ed63 | 2021-07-26 13:44:19 +0000 | [diff] [blame] | 86 | .latency = C_STATE_LATENCY_FROM_LAT_REG(3), |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 87 | .power = C8_POWER, |
| 88 | .resource = MWAIT_RES(4, 0), |
| 89 | }, |
| 90 | [C_STATE_C9] = { |
Nico Huber | 792ed63 | 2021-07-26 13:44:19 +0000 | [diff] [blame] | 91 | .latency = C_STATE_LATENCY_FROM_LAT_REG(4), |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 92 | .power = C9_POWER, |
| 93 | .resource = MWAIT_RES(5, 0), |
| 94 | }, |
| 95 | [C_STATE_C10] = { |
Nico Huber | 792ed63 | 2021-07-26 13:44:19 +0000 | [diff] [blame] | 96 | .latency = C_STATE_LATENCY_FROM_LAT_REG(5), |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 97 | .power = C10_POWER, |
| 98 | .resource = MWAIT_RES(6, 0), |
| 99 | }, |
| 100 | }; |
| 101 | |
Ronak Kanabar | c6c4d00 | 2019-01-30 18:53:14 +0530 | [diff] [blame] | 102 | static int cstate_set_non_s0ix[] = { |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 103 | C_STATE_C1E, |
| 104 | C_STATE_C6_LONG_LAT, |
| 105 | C_STATE_C7S_LONG_LAT |
| 106 | }; |
| 107 | |
Ronak Kanabar | c6c4d00 | 2019-01-30 18:53:14 +0530 | [diff] [blame] | 108 | static int cstate_set_s0ix[] = { |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 109 | C_STATE_C1E, |
| 110 | C_STATE_C7S_LONG_LAT, |
| 111 | C_STATE_C10 |
| 112 | }; |
| 113 | |
Angel Pons | e9f10ff | 2021-10-17 13:28:23 +0200 | [diff] [blame] | 114 | const acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 115 | { |
| 116 | static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), |
| 117 | ARRAY_SIZE(cstate_set_non_s0ix))]; |
| 118 | int *set; |
| 119 | int i; |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 120 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 121 | config_t *config = config_of_soc(); |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 122 | |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 123 | int is_s0ix_enable = config->s0ix_enable; |
| 124 | |
| 125 | if (is_s0ix_enable) { |
| 126 | *entries = ARRAY_SIZE(cstate_set_s0ix); |
| 127 | set = cstate_set_s0ix; |
| 128 | } else { |
| 129 | *entries = ARRAY_SIZE(cstate_set_non_s0ix); |
| 130 | set = cstate_set_non_s0ix; |
| 131 | } |
| 132 | |
| 133 | for (i = 0; i < *entries; i++) { |
Angel Pons | 14643b3 | 2021-10-17 13:21:05 +0200 | [diff] [blame] | 134 | map[i] = cstate_map[set[i]]; |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 135 | map[i].ctype = i + 1; |
| 136 | } |
| 137 | return map; |
| 138 | } |
| 139 | |
| 140 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 141 | { |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 142 | config_t *config = config_of_soc(); |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 143 | |
| 144 | /* Generate P-state tables */ |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 145 | if (config->eist_enable) |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame] | 146 | generate_p_state_entries(core_id, cores_per_package); |
| 147 | } |
| 148 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 149 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 150 | { |
| 151 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 152 | const struct soc_intel_cannonlake_config *config; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 153 | config = config_of_soc(); |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 154 | |
Meera Ravindranath | 48c7870 | 2019-12-12 10:37:49 +0530 | [diff] [blame] | 155 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 156 | fadt->pm_tmr_len = 4; |
Kyösti Mälkki | 88decca | 2023-04-28 07:04:34 +0300 | [diff] [blame] | 157 | |
| 158 | fill_fadt_extended_pm_io(fadt); |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 159 | |
Duncan Laurie | 174ca43 | 2018-09-13 16:28:13 +0000 | [diff] [blame] | 160 | if (config->s0ix_enable) |
Vaibhav Shankar | 2da6ec4 | 2018-03-19 18:56:38 -0700 | [diff] [blame] | 161 | fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 162 | } |
Matt DeVillier | b065e81 | 2023-10-21 20:44:58 -0500 | [diff] [blame] | 163 | |
| 164 | static struct min_sleep_state min_pci_sleep_states[] = { |
| 165 | { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 }, |
| 166 | { SA_DEVFN_PEG0, ACPI_DEVICE_SLEEP_D3 }, |
| 167 | { SA_DEVFN_PEG1, ACPI_DEVICE_SLEEP_D3 }, |
| 168 | { SA_DEVFN_PEG2, ACPI_DEVICE_SLEEP_D3 }, |
| 169 | { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 }, |
| 170 | { SA_DEVFN_TS, ACPI_DEVICE_SLEEP_D3 }, |
| 171 | { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 }, |
| 172 | { SA_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 }, |
| 173 | { PCH_DEVFN_UFS, ACPI_DEVICE_SLEEP_D3 }, |
| 174 | { PCH_DEVFN_GSPI2, ACPI_DEVICE_SLEEP_D3 }, |
| 175 | { PCH_DEVFN_ISH, ACPI_DEVICE_SLEEP_D3 }, |
| 176 | { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 }, |
| 177 | { PCH_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 }, |
| 178 | { PCH_DEVFN_CNViWIFI, ACPI_DEVICE_SLEEP_D3 }, |
| 179 | { PCH_DEVFN_SDCARD, ACPI_DEVICE_SLEEP_D3 }, |
| 180 | { PCH_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 }, |
| 181 | { PCH_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 }, |
| 182 | { PCH_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 }, |
| 183 | { PCH_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 }, |
| 184 | { PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 }, |
| 185 | { PCH_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 }, |
| 186 | { PCH_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 }, |
| 187 | { PCH_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 }, |
| 188 | { PCH_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 }, |
| 189 | { PCH_DEVFN_EMMC, ACPI_DEVICE_SLEEP_D3 }, |
| 190 | { PCH_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 }, |
| 191 | { PCH_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 }, |
| 192 | { PCH_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 }, |
| 193 | { PCH_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 }, |
| 194 | { PCH_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 }, |
| 195 | { PCH_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 }, |
| 196 | { PCH_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 }, |
| 197 | { PCH_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 }, |
| 198 | { PCH_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 }, |
| 199 | { PCH_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 }, |
| 200 | { PCH_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 }, |
| 201 | { PCH_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 }, |
| 202 | { PCH_DEVFN_PCIE13, ACPI_DEVICE_SLEEP_D0 }, |
| 203 | { PCH_DEVFN_PCIE14, ACPI_DEVICE_SLEEP_D0 }, |
| 204 | { PCH_DEVFN_PCIE15, ACPI_DEVICE_SLEEP_D0 }, |
| 205 | { PCH_DEVFN_PCIE16, ACPI_DEVICE_SLEEP_D0 }, |
| 206 | { PCH_DEVFN_PCIE17, ACPI_DEVICE_SLEEP_D0 }, |
| 207 | { PCH_DEVFN_PCIE18, ACPI_DEVICE_SLEEP_D0 }, |
| 208 | { PCH_DEVFN_PCIE19, ACPI_DEVICE_SLEEP_D0 }, |
| 209 | { PCH_DEVFN_PCIE20, ACPI_DEVICE_SLEEP_D0 }, |
| 210 | { PCH_DEVFN_PCIE21, ACPI_DEVICE_SLEEP_D0 }, |
| 211 | { PCH_DEVFN_PCIE22, ACPI_DEVICE_SLEEP_D0 }, |
| 212 | { PCH_DEVFN_PCIE23, ACPI_DEVICE_SLEEP_D0 }, |
| 213 | { PCH_DEVFN_PCIE24, ACPI_DEVICE_SLEEP_D0 }, |
| 214 | { PCH_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 }, |
| 215 | { PCH_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 }, |
| 216 | { PCH_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 }, |
| 217 | { PCH_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 }, |
| 218 | { PCH_DEVFN_LPC, ACPI_DEVICE_SLEEP_D0 }, |
| 219 | { PCH_DEVFN_P2SB, ACPI_DEVICE_SLEEP_D0 }, |
| 220 | { PCH_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, |
| 221 | { PCH_DEVFN_SMBUS, ACPI_DEVICE_SLEEP_D0 }, |
| 222 | { PCH_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, |
| 223 | { PCH_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, |
| 224 | { PCH_DEVFN_TRACEHUB, ACPI_DEVICE_SLEEP_D3 }, |
| 225 | }; |
| 226 | |
| 227 | struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size) |
| 228 | { |
| 229 | *size = ARRAY_SIZE(min_pci_sleep_states); |
| 230 | return min_pci_sleep_states; |
| 231 | } |
| 232 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 233 | uint32_t soc_read_sci_irq_select(void) |
| 234 | { |
Angel Pons | f585c6e | 2021-06-25 10:09:35 +0200 | [diff] [blame] | 235 | return read32p(soc_read_pmc_base() + IRQ_REG); |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 236 | } |
| 237 | |
Kyösti Mälkki | c2b0a4f | 2020-06-28 22:39:59 +0300 | [diff] [blame] | 238 | void soc_fill_gnvs(struct global_nvs *gnvs) |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 239 | { |
Kyösti Mälkki | 28dc7dc | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 240 | const struct soc_intel_cannonlake_config *config; |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 241 | config = config_of_soc(); |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 242 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 243 | /* Enable DPTF based on mainboard configuration */ |
| 244 | gnvs->dpte = config->dptf_enable; |
| 245 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 246 | /* Set USB2/USB3 wake enable bitmaps. */ |
| 247 | gnvs->u2we = config->usb2_wake_enable_bitmap; |
| 248 | gnvs->u3we = config->usb3_wake_enable_bitmap; |
| 249 | } |
| 250 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 251 | int soc_madt_sci_irq_polarity(int sci) |
| 252 | { |
| 253 | return MP_IRQ_POLARITY_HIGH; |
| 254 | } |
Lijian Zhao | 5ff742c | 2018-12-27 17:01:09 -0800 | [diff] [blame] | 255 | |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 256 | static unsigned long soc_fill_dmar(unsigned long current) |
| 257 | { |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 258 | struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 259 | uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; |
| 260 | bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; |
Patrick Rudolph | a9eec2c | 2020-07-28 12:05:17 +0200 | [diff] [blame] | 261 | const bool emit_igd = igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten; |
| 262 | if (emit_igd) { |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 263 | unsigned long tmp = current; |
| 264 | |
| 265 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
| 266 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 267 | |
| 268 | acpi_dmar_drhd_fixup(tmp, current); |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 269 | } |
| 270 | |
Kyösti Mälkki | 903b40a | 2019-07-03 07:25:59 +0300 | [diff] [blame] | 271 | struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 272 | uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; |
| 273 | bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; |
| 274 | |
| 275 | if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) { |
| 276 | unsigned long tmp = current; |
| 277 | |
| 278 | current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar); |
| 279 | current += acpi_create_dmar_ds_pci(current, 0, 5, 0); |
| 280 | |
| 281 | acpi_dmar_drhd_fixup(tmp, current); |
| 282 | } |
| 283 | |
| 284 | uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK; |
| 285 | bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED; |
| 286 | |
| 287 | if (vtvc0bar && vtvc0en) { |
| 288 | const unsigned long tmp = current; |
| 289 | |
| 290 | current += acpi_create_dmar_drhd(current, |
| 291 | DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); |
Arthur Heymans | d90154c | 2022-12-02 13:27:35 +0100 | [diff] [blame] | 292 | current += acpi_create_dmar_ds_ioapic_from_hw(current, |
| 293 | IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 294 | V_P2SB_CFG_IBDF_FUNC); |
| 295 | current += acpi_create_dmar_ds_msi_hpet(current, |
| 296 | 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, |
| 297 | V_P2SB_CFG_HBDF_FUNC); |
| 298 | |
| 299 | acpi_dmar_drhd_fixup(tmp, current); |
| 300 | } |
| 301 | |
Patrick Rudolph | a9eec2c | 2020-07-28 12:05:17 +0200 | [diff] [blame] | 302 | /* Add RMRR entry after all DRHD entries */ |
| 303 | if (emit_igd) { |
| 304 | const unsigned long tmp = current; |
| 305 | |
| 306 | current += acpi_create_dmar_rmrr(current, 0, |
| 307 | sa_get_gsm_base(), sa_get_tolud_base() - 1); |
| 308 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 309 | acpi_dmar_rmrr_fixup(tmp, current); |
| 310 | } |
John Zhao | 1159a16 | 2019-04-22 10:45:51 -0700 | [diff] [blame] | 311 | |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 312 | return current; |
| 313 | } |
| 314 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 315 | unsigned long sa_write_acpi_tables(const struct device *dev, unsigned long current, |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 316 | struct acpi_rsdp *rsdp) |
| 317 | { |
| 318 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 319 | |
| 320 | /* Create DMAR table only if we have VT-d capability |
| 321 | * and FSP does not override its feature. |
| 322 | */ |
| 323 | if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) || |
| 324 | !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED)) |
| 325 | return current; |
| 326 | |
| 327 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 328 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, soc_fill_dmar); |
John Zhao | 1159a16 | 2019-04-22 10:45:51 -0700 | [diff] [blame] | 329 | |
John Zhao | db3f0e3 | 2019-03-15 16:54:27 -0700 | [diff] [blame] | 330 | current += dmar->header.length; |
| 331 | current = acpi_align_current(current); |
| 332 | acpi_add_table(rsdp, dmar); |
| 333 | |
| 334 | return current; |
| 335 | } |