Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * Copyright (C) 2017 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <arch/acpi.h> |
| 19 | #include <arch/acpigen.h> |
| 20 | #include <arch/cpu.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <arch/ioapic.h> |
| 23 | #include <arch/smp/mpspec.h> |
| 24 | #include <cbmem.h> |
| 25 | #include <chip.h> |
| 26 | #include <cpu/cpu.h> |
| 27 | #include <ec/google/chromeec/ec.h> |
| 28 | #include <intelblocks/cpulib.h> |
| 29 | #include <intelblocks/pmclib.h> |
| 30 | #include <intelblocks/acpi.h> |
| 31 | #include <soc/cpu.h> |
| 32 | #include <soc/iomap.h> |
| 33 | #include <soc/nvs.h> |
| 34 | #include <soc/pci_devs.h> |
| 35 | #include <soc/pm.h> |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame^] | 36 | #include <string.h> |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 37 | #include <vendorcode/google/chromeos/gnvs.h> |
| 38 | #include <wrdd.h> |
| 39 | |
Shaunak Saha | 95b6175 | 2017-10-04 23:08:40 -0700 | [diff] [blame^] | 40 | /* |
| 41 | * List of supported C-states in this processor. |
| 42 | */ |
| 43 | enum { |
| 44 | C_STATE_C0, /* 0 */ |
| 45 | C_STATE_C1, /* 1 */ |
| 46 | C_STATE_C1E, /* 2 */ |
| 47 | C_STATE_C6_SHORT_LAT, /* 3 */ |
| 48 | C_STATE_C6_LONG_LAT, /* 4 */ |
| 49 | C_STATE_C7_SHORT_LAT, /* 5 */ |
| 50 | C_STATE_C7_LONG_LAT, /* 6 */ |
| 51 | C_STATE_C7S_SHORT_LAT, /* 7 */ |
| 52 | C_STATE_C7S_LONG_LAT, /* 8 */ |
| 53 | C_STATE_C8, /* 9 */ |
| 54 | C_STATE_C9, /* 10 */ |
| 55 | C_STATE_C10, /* 11 */ |
| 56 | NUM_C_STATES |
| 57 | }; |
| 58 | |
| 59 | #define MWAIT_RES(state, sub_state) \ |
| 60 | { \ |
| 61 | .addrl = (((state) << 4) | (sub_state)), \ |
| 62 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 63 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 64 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 65 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 66 | } |
| 67 | |
| 68 | static const acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 69 | [C_STATE_C0] = {}, |
| 70 | [C_STATE_C1] = { |
| 71 | .latency = 0, |
| 72 | .power = C1_POWER, |
| 73 | .resource = MWAIT_RES(0, 0), |
| 74 | }, |
| 75 | [C_STATE_C1E] = { |
| 76 | .latency = 0, |
| 77 | .power = C1_POWER, |
| 78 | .resource = MWAIT_RES(0, 1), |
| 79 | }, |
| 80 | [C_STATE_C6_SHORT_LAT] = { |
| 81 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 82 | .power = C6_POWER, |
| 83 | .resource = MWAIT_RES(2, 0), |
| 84 | }, |
| 85 | [C_STATE_C6_LONG_LAT] = { |
| 86 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 87 | .power = C6_POWER, |
| 88 | .resource = MWAIT_RES(2, 1), |
| 89 | }, |
| 90 | [C_STATE_C7_SHORT_LAT] = { |
| 91 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 92 | .power = C7_POWER, |
| 93 | .resource = MWAIT_RES(3, 0), |
| 94 | }, |
| 95 | [C_STATE_C7_LONG_LAT] = { |
| 96 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 97 | .power = C7_POWER, |
| 98 | .resource = MWAIT_RES(3, 1), |
| 99 | }, |
| 100 | [C_STATE_C7S_SHORT_LAT] = { |
| 101 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 102 | .power = C7_POWER, |
| 103 | .resource = MWAIT_RES(3, 2), |
| 104 | }, |
| 105 | [C_STATE_C7S_LONG_LAT] = { |
| 106 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 107 | .power = C7_POWER, |
| 108 | .resource = MWAIT_RES(3, 3), |
| 109 | }, |
| 110 | [C_STATE_C8] = { |
| 111 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 112 | .power = C8_POWER, |
| 113 | .resource = MWAIT_RES(4, 0), |
| 114 | }, |
| 115 | [C_STATE_C9] = { |
| 116 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 117 | .power = C9_POWER, |
| 118 | .resource = MWAIT_RES(5, 0), |
| 119 | }, |
| 120 | [C_STATE_C10] = { |
| 121 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 122 | .power = C10_POWER, |
| 123 | .resource = MWAIT_RES(6, 0), |
| 124 | }, |
| 125 | }; |
| 126 | |
| 127 | static int cstate_set_s0ix[] = { |
| 128 | C_STATE_C1E, |
| 129 | C_STATE_C6_LONG_LAT, |
| 130 | C_STATE_C7S_LONG_LAT |
| 131 | }; |
| 132 | |
| 133 | static int cstate_set_non_s0ix[] = { |
| 134 | C_STATE_C1E, |
| 135 | C_STATE_C7S_LONG_LAT, |
| 136 | C_STATE_C10 |
| 137 | }; |
| 138 | |
| 139 | acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
| 140 | { |
| 141 | static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix), |
| 142 | ARRAY_SIZE(cstate_set_non_s0ix))]; |
| 143 | int *set; |
| 144 | int i; |
| 145 | device_t dev = SA_DEV_ROOT; |
| 146 | config_t *config = dev->chip_info; |
| 147 | int is_s0ix_enable = config->s0ix_enable; |
| 148 | |
| 149 | if (is_s0ix_enable) { |
| 150 | *entries = ARRAY_SIZE(cstate_set_s0ix); |
| 151 | set = cstate_set_s0ix; |
| 152 | } else { |
| 153 | *entries = ARRAY_SIZE(cstate_set_non_s0ix); |
| 154 | set = cstate_set_non_s0ix; |
| 155 | } |
| 156 | |
| 157 | for (i = 0; i < *entries; i++) { |
| 158 | memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t)); |
| 159 | map[i].ctype = i + 1; |
| 160 | } |
| 161 | return map; |
| 162 | } |
| 163 | |
| 164 | void soc_power_states_generation(int core_id, int cores_per_package) |
| 165 | { |
| 166 | device_t dev = SA_DEV_ROOT; |
| 167 | config_t *config = dev->chip_info; |
| 168 | if (config->eist_enable) |
| 169 | /* Generate P-state tables */ |
| 170 | generate_p_state_entries(core_id, cores_per_package); |
| 171 | } |
| 172 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 173 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 174 | { |
| 175 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 176 | const struct device *dev = PCH_DEV_LPC; |
| 177 | const struct soc_intel_cannonlake_config *config = dev->chip_info; |
| 178 | |
| 179 | if (config->PmTimerDisabled != 0) |
| 180 | return; |
| 181 | |
| 182 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 183 | fadt->pm_tmr_len = 4; |
| 184 | fadt->x_pm_tmr_blk.space_id = 1; |
| 185 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 186 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 187 | fadt->x_pm_tmr_blk.resv = 0; |
| 188 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 189 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 190 | } |
| 191 | uint32_t soc_read_sci_irq_select(void) |
| 192 | { |
| 193 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 194 | return read32((void *)pmc_bar + IRQ_REG); |
| 195 | } |
| 196 | |
| 197 | void acpi_create_gnvs(struct global_nvs_t *gnvs) |
| 198 | { |
| 199 | const struct device *dev = PCH_DEV_LPC; |
| 200 | const struct soc_intel_cannonlake_config *config = dev->chip_info; |
| 201 | |
| 202 | /* Set unknown wake source */ |
| 203 | gnvs->pm1i = -1; |
| 204 | |
| 205 | /* CPU core count */ |
| 206 | gnvs->pcnt = dev_count_cpu(); |
| 207 | |
| 208 | if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) |
| 209 | /* Update the mem console pointer. */ |
| 210 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 211 | |
| 212 | if (IS_ENABLED(CONFIG_CHROMEOS)) { |
| 213 | /* Initialize Verified Boot data */ |
| 214 | chromeos_init_vboot(&(gnvs->chromeos)); |
| 215 | if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { |
| 216 | gnvs->chromeos.vbt2 = google_ec_running_ro() ? |
| 217 | ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; |
| 218 | } else |
| 219 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 220 | } |
| 221 | |
| 222 | /* Enable DPTF based on mainboard configuration */ |
| 223 | gnvs->dpte = config->dptf_enable; |
| 224 | |
| 225 | /* Fill in the Wifi Region id */ |
| 226 | gnvs->cid1 = wifi_regulatory_domain(); |
| 227 | |
| 228 | /* Set USB2/USB3 wake enable bitmaps. */ |
| 229 | gnvs->u2we = config->usb2_wake_enable_bitmap; |
| 230 | gnvs->u3we = config->usb3_wake_enable_bitmap; |
| 231 | } |
| 232 | |
| 233 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 234 | const struct chipset_power_state *ps) |
| 235 | { |
| 236 | /* |
| 237 | * WAK_STS bit is set when the system is in one of the sleep states |
| 238 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 239 | * this bit, the PMC will transition the system to the ON state and |
| 240 | * can only be set by hardware and can only be cleared by writing a one |
| 241 | * to this bit position. |
| 242 | */ |
| 243 | |
| 244 | generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; |
| 245 | return generic_pm1_en; |
| 246 | } |
| 247 | |
| 248 | int soc_madt_sci_irq_polarity(int sci) |
| 249 | { |
| 250 | return MP_IRQ_POLARITY_HIGH; |
| 251 | } |