soc/intel/cannonlake: Implement SoC sleep state array
Adapted from Alderlake implementation, modified as needed.
Device names missing from soc_acpi_name() were added as well.
TEST=build/boot Win11, Linux on google/hatch (akemi).
Change-Id: Ib2c733c04e29f0f9e7e2e6dbf36c2a7618fdc23f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index 62462a8..ff93e2a 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -160,6 +160,76 @@
if (config->s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
}
+
+static struct min_sleep_state min_pci_sleep_states[] = {
+ { SA_DEVFN_ROOT, ACPI_DEVICE_SLEEP_D3 },
+ { SA_DEVFN_PEG0, ACPI_DEVICE_SLEEP_D3 },
+ { SA_DEVFN_PEG1, ACPI_DEVICE_SLEEP_D3 },
+ { SA_DEVFN_PEG2, ACPI_DEVICE_SLEEP_D3 },
+ { SA_DEVFN_IGD, ACPI_DEVICE_SLEEP_D3 },
+ { SA_DEVFN_TS, ACPI_DEVICE_SLEEP_D3 },
+ { SA_DEVFN_IPU, ACPI_DEVICE_SLEEP_D3 },
+ { SA_DEVFN_GNA, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_UFS, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_GSPI2, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_ISH, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_XHCI, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_USBOTG, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_CNViWIFI, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_SDCARD, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_I2C0, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_I2C1, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_I2C2, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_I2C3, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_CSE, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_SATA, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_I2C4, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_I2C5, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_UART2, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_EMMC, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_PCIE1, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE2, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE3, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE4, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE5, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE6, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE7, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE8, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE9, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE10, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE11, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE12, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE13, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE14, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE15, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE16, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE17, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE18, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE19, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE20, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE21, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE22, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE23, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_PCIE24, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_UART0, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_UART1, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_GSPI0, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_GSPI1, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_LPC, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_P2SB, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_SMBUS, ACPI_DEVICE_SLEEP_D0 },
+ { PCH_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 },
+ { PCH_DEVFN_TRACEHUB, ACPI_DEVICE_SLEEP_D3 },
+};
+
+struct min_sleep_state *soc_get_min_sleep_state_array(size_t *size)
+{
+ *size = ARRAY_SIZE(min_pci_sleep_states);
+ return min_pci_sleep_states;
+}
+
uint32_t soc_read_sci_irq_select(void)
{
return read32p(soc_read_pmc_base() + IRQ_REG);