Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * Copyright (C) 2017 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <arch/acpi.h> |
| 19 | #include <arch/acpigen.h> |
| 20 | #include <arch/cpu.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <arch/ioapic.h> |
| 23 | #include <arch/smp/mpspec.h> |
| 24 | #include <cbmem.h> |
| 25 | #include <chip.h> |
| 26 | #include <cpu/cpu.h> |
| 27 | #include <ec/google/chromeec/ec.h> |
| 28 | #include <intelblocks/cpulib.h> |
| 29 | #include <intelblocks/pmclib.h> |
| 30 | #include <intelblocks/acpi.h> |
| 31 | #include <soc/cpu.h> |
| 32 | #include <soc/iomap.h> |
| 33 | #include <soc/nvs.h> |
| 34 | #include <soc/pci_devs.h> |
| 35 | #include <soc/pm.h> |
| 36 | #include <vendorcode/google/chromeos/gnvs.h> |
| 37 | #include <wrdd.h> |
| 38 | |
| 39 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 40 | { |
| 41 | const uint16_t pmbase = ACPI_BASE_ADDRESS; |
| 42 | const struct device *dev = PCH_DEV_LPC; |
| 43 | const struct soc_intel_cannonlake_config *config = dev->chip_info; |
| 44 | |
| 45 | if (config->PmTimerDisabled != 0) |
| 46 | return; |
| 47 | |
| 48 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 49 | fadt->pm_tmr_len = 4; |
| 50 | fadt->x_pm_tmr_blk.space_id = 1; |
| 51 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 52 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 53 | fadt->x_pm_tmr_blk.resv = 0; |
| 54 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 55 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 56 | } |
| 57 | uint32_t soc_read_sci_irq_select(void) |
| 58 | { |
| 59 | uintptr_t pmc_bar = soc_read_pmc_base(); |
| 60 | return read32((void *)pmc_bar + IRQ_REG); |
| 61 | } |
| 62 | |
| 63 | void acpi_create_gnvs(struct global_nvs_t *gnvs) |
| 64 | { |
| 65 | const struct device *dev = PCH_DEV_LPC; |
| 66 | const struct soc_intel_cannonlake_config *config = dev->chip_info; |
| 67 | |
| 68 | /* Set unknown wake source */ |
| 69 | gnvs->pm1i = -1; |
| 70 | |
| 71 | /* CPU core count */ |
| 72 | gnvs->pcnt = dev_count_cpu(); |
| 73 | |
| 74 | if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) |
| 75 | /* Update the mem console pointer. */ |
| 76 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 77 | |
| 78 | if (IS_ENABLED(CONFIG_CHROMEOS)) { |
| 79 | /* Initialize Verified Boot data */ |
| 80 | chromeos_init_vboot(&(gnvs->chromeos)); |
| 81 | if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { |
| 82 | gnvs->chromeos.vbt2 = google_ec_running_ro() ? |
| 83 | ACTIVE_ECFW_RO : ACTIVE_ECFW_RW; |
| 84 | } else |
| 85 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 86 | } |
| 87 | |
| 88 | /* Enable DPTF based on mainboard configuration */ |
| 89 | gnvs->dpte = config->dptf_enable; |
| 90 | |
| 91 | /* Fill in the Wifi Region id */ |
| 92 | gnvs->cid1 = wifi_regulatory_domain(); |
| 93 | |
| 94 | /* Set USB2/USB3 wake enable bitmaps. */ |
| 95 | gnvs->u2we = config->usb2_wake_enable_bitmap; |
| 96 | gnvs->u3we = config->usb3_wake_enable_bitmap; |
| 97 | } |
| 98 | |
| 99 | uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en, |
| 100 | const struct chipset_power_state *ps) |
| 101 | { |
| 102 | /* |
| 103 | * WAK_STS bit is set when the system is in one of the sleep states |
| 104 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 105 | * this bit, the PMC will transition the system to the ON state and |
| 106 | * can only be set by hardware and can only be cleared by writing a one |
| 107 | * to this bit position. |
| 108 | */ |
| 109 | |
| 110 | generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; |
| 111 | return generic_pm1_en; |
| 112 | } |
| 113 | |
| 114 | int soc_madt_sci_irq_polarity(int sci) |
| 115 | { |
| 116 | return MP_IRQ_POLARITY_HIGH; |
| 117 | } |