Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 4 | * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com> |
| 5 | * Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 6 | * Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 19 | #include <commonlib/region.h> |
Kyösti Mälkki | 5687fc9 | 2013-11-28 18:11:49 +0200 | [diff] [blame] | 20 | #include <bootmode.h> |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 21 | #include <cf9_reset.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 22 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 23 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 24 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 25 | #include <device/pci_ops.h> |
Kyösti Mälkki | 1cae454 | 2020-01-06 12:31:34 +0200 | [diff] [blame^] | 26 | #include <device/smbus_host.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 27 | #include <cbmem.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 28 | #include <timestamp.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 29 | #include <mrc_cache.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 30 | #include <southbridge/intel/bd82x6x/me.h> |
Patrick Rudolph | da9302a | 2019-03-24 17:01:41 +0100 | [diff] [blame] | 31 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 32 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 33 | #include <types.h> |
Elyes HAOUAS | bf0970e | 2019-03-21 11:10:03 +0100 | [diff] [blame] | 34 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 35 | #include "raminit_native.h" |
| 36 | #include "raminit_common.h" |
| 37 | #include "sandybridge.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 38 | |
Patrick Rudolph | 708cf4b | 2018-07-29 12:34:03 +0200 | [diff] [blame] | 39 | #define MRC_CACHE_VERSION 1 |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 40 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 41 | /* FIXME: no ECC support. */ |
| 42 | /* FIXME: no support for 3-channel chipsets. */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 43 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 44 | static const char *ecc_decoder[] = { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 45 | "inactive", |
| 46 | "active on IO", |
| 47 | "disabled on IO", |
| 48 | "active" |
| 49 | }; |
| 50 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 51 | static void wait_txt_clear(void) |
| 52 | { |
| 53 | struct cpuid_result cp; |
| 54 | |
| 55 | cp = cpuid_ext(0x1, 0x0); |
| 56 | /* Check if TXT is supported? */ |
| 57 | if (!(cp.ecx & 0x40)) |
| 58 | return; |
| 59 | /* Some TXT public bit. */ |
| 60 | if (!(read32((void *)0xfed30010) & 1)) |
| 61 | return; |
| 62 | /* Wait for TXT clear. */ |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 63 | while (!(read8((void *)0xfed40000) & (1 << 7))); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 64 | } |
| 65 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 66 | /* |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 67 | * Disable a channel in ramctr_timing. |
| 68 | */ |
| 69 | static void disable_channel(ramctr_timing *ctrl, int channel) { |
| 70 | ctrl->rankmap[channel] = 0; |
| 71 | memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); |
| 72 | ctrl->channel_size_mb[channel] = 0; |
| 73 | ctrl->cmd_stretch[channel] = 0; |
| 74 | ctrl->mad_dimm[channel] = 0; |
| 75 | memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); |
Patrick Rudolph | 74163d6 | 2016-11-17 20:02:43 +0100 | [diff] [blame] | 76 | memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | /* |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 80 | * Fill cbmem with information for SMBIOS type 17. |
| 81 | */ |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 82 | static void fill_smbios17(ramctr_timing *ctrl) |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 83 | { |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 84 | int channel, slot; |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 85 | const u16 ddr_freq = (1000 << 8) / ctrl->tCK; |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 86 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 87 | FOR_ALL_CHANNELS for (slot = 0; slot < NUM_SLOTS; slot++) { |
Patrick Rudolph | 24efe73 | 2018-08-19 11:06:06 +0200 | [diff] [blame] | 88 | enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq, |
| 89 | &ctrl->info.dimm[channel][slot]); |
| 90 | if (ret != CB_SUCCESS) |
| 91 | printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n"); |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 92 | } |
| 93 | } |
| 94 | |
| 95 | /* |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 96 | * Dump in the log memory controller configuration as read from the memory |
| 97 | * controller registers. |
| 98 | */ |
| 99 | static void report_memory_config(void) |
| 100 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 101 | u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; |
Patrick Rudolph | 6ab7e5e | 2017-05-31 18:21:59 +0200 | [diff] [blame] | 102 | int i, refclk; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 103 | |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 104 | addr_decoder_common = MCHBAR32(MAD_CHNL); |
| 105 | addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); |
| 106 | addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 107 | |
Patrick Rudolph | 6ab7e5e | 2017-05-31 18:21:59 +0200 | [diff] [blame] | 108 | refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; |
| 109 | |
| 110 | printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 111 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
Patrick Rudolph | 6ab7e5e | 2017-05-31 18:21:59 +0200 | [diff] [blame] | 112 | (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 113 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 114 | addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 115 | (addr_decoder_common >> 4) & 3); |
| 116 | |
| 117 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 118 | u32 ch_conf = addr_decode_ch[i]; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 119 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, |
| 120 | ch_conf); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 121 | printk(BIOS_DEBUG, " ECC %s\n", |
| 122 | ecc_decoder[(ch_conf >> 24) & 3]); |
| 123 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 124 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 125 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 126 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
| 127 | printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", |
| 128 | ((ch_conf >> 0) & 0xff) * 256, |
| 129 | ((ch_conf >> 19) & 1) ? 16 : 8, |
| 130 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 131 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 132 | printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", |
| 133 | ((ch_conf >> 8) & 0xff) * 256, |
| 134 | ((ch_conf >> 20) & 1) ? 16 : 8, |
| 135 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 136 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 137 | } |
| 138 | } |
| 139 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 140 | /* |
| 141 | * Return CRC16 match for all SPDs. |
| 142 | */ |
| 143 | static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) |
| 144 | { |
| 145 | int channel, slot, spd_slot; |
| 146 | int match = 1; |
| 147 | |
| 148 | FOR_ALL_CHANNELS { |
| 149 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 150 | spd_slot = 2 * channel + slot; |
| 151 | match &= ctrl->spd_crc[channel][slot] == |
Kyösti Mälkki | fc5d85c | 2016-11-18 18:52:04 +0200 | [diff] [blame] | 152 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 153 | } |
| 154 | } |
| 155 | return match; |
| 156 | } |
| 157 | |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 158 | void read_spd(spd_raw_data * spd, u8 addr, bool id_only) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 159 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 160 | int j; |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 161 | if (id_only) { |
| 162 | for (j = 117; j < 128; j++) |
| 163 | (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j); |
| 164 | } else { |
| 165 | for (j = 0; j < 256; j++) |
| 166 | (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j); |
| 167 | } |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 168 | } |
| 169 | |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 170 | static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 171 | { |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 172 | int dimms = 0, dimms_on_channel; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 173 | int channel, slot, spd_slot; |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 174 | dimm_info *dimm = &ctrl->info; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 175 | |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 176 | memset (ctrl->rankmap, 0, sizeof(ctrl->rankmap)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 177 | |
| 178 | ctrl->extended_temperature_range = 1; |
| 179 | ctrl->auto_self_refresh = 1; |
| 180 | |
| 181 | FOR_ALL_CHANNELS { |
| 182 | ctrl->channel_size_mb[channel] = 0; |
| 183 | |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 184 | dimms_on_channel = 0; |
| 185 | /* count dimms on channel */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 186 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 187 | spd_slot = 2 * channel + slot; |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 188 | printk(BIOS_DEBUG, |
| 189 | "SPD probe channel%d, slot%d\n", channel, slot); |
| 190 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 191 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 192 | if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 193 | dimms_on_channel++; |
| 194 | } |
| 195 | |
| 196 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 197 | spd_slot = 2 * channel + slot; |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 198 | printk(BIOS_DEBUG, |
| 199 | "SPD probe channel%d, slot%d\n", channel, slot); |
| 200 | |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 201 | /* search for XMP profile */ |
| 202 | spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], |
| 203 | spd[spd_slot], |
| 204 | DDR3_XMP_PROFILE_1); |
| 205 | |
| 206 | if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
| 207 | printram("No valid XMP profile found.\n"); |
| 208 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
| 209 | } else if (dimms_on_channel > dimm->dimm[channel][slot].dimms_per_channel) { |
| 210 | printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", |
| 211 | dimm->dimm[channel][slot].dimms_per_channel, |
| 212 | dimms_on_channel); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 213 | if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) |
Vagiz Trakhanov | 771be48 | 2017-10-02 10:02:35 +0000 | [diff] [blame] | 214 | printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n"); |
| 215 | else |
| 216 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 217 | } else if (dimm->dimm[channel][slot].voltage != 1500) { |
| 218 | /* TODO: support other DDR3 voltage than 1500mV */ |
| 219 | printram("XMP profile's requested %u mV is unsupported.\n", |
| 220 | dimm->dimm[channel][slot].voltage); |
| 221 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
| 222 | } |
| 223 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 224 | /* fill in CRC16 for MRC cache */ |
| 225 | ctrl->spd_crc[channel][slot] = |
Kyösti Mälkki | fc5d85c | 2016-11-18 18:52:04 +0200 | [diff] [blame] | 226 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 227 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 228 | if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
| 229 | // set dimm invalid |
| 230 | dimm->dimm[channel][slot].ranks = 0; |
| 231 | dimm->dimm[channel][slot].size_mb = 0; |
| 232 | continue; |
| 233 | } |
| 234 | |
| 235 | dram_print_spd_ddr3(&dimm->dimm[channel][slot]); |
| 236 | dimms++; |
| 237 | ctrl->rank_mirror[channel][slot * 2] = 0; |
| 238 | ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->dimm[channel][slot].flags.pins_mirrored; |
| 239 | ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb; |
| 240 | |
| 241 | ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr; |
| 242 | ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh; |
| 243 | |
| 244 | ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); |
Patrick Rudolph | a649a54 | 2016-01-17 18:32:06 +0100 | [diff] [blame] | 245 | printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", |
| 246 | channel, ctrl->rankmap[channel]); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 247 | } |
| 248 | if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc) |
| 249 | && dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) { |
| 250 | const int ref_card_offset_table[6][6] = { |
| 251 | { 0, 0, 0, 0, 2, 2, }, |
| 252 | { 0, 0, 0, 0, 2, 2, }, |
| 253 | { 0, 0, 0, 0, 2, 2, }, |
| 254 | { 0, 0, 0, 0, 1, 1, }, |
| 255 | { 2, 2, 2, 1, 0, 0, }, |
| 256 | { 2, 2, 2, 1, 0, 0, }, |
| 257 | }; |
| 258 | ctrl->ref_card_offset[channel] = ref_card_offset_table[dimm->dimm[channel][0].reference_card] |
| 259 | [dimm->dimm[channel][1].reference_card]; |
| 260 | } else |
| 261 | ctrl->ref_card_offset[channel] = 0; |
| 262 | } |
| 263 | |
| 264 | if (!dimms) |
| 265 | die("No DIMMs were found"); |
| 266 | } |
| 267 | |
Patrick Rudolph | bb9c90a | 2016-05-29 17:05:06 +0200 | [diff] [blame] | 268 | static void save_timings(ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 269 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 270 | /* Save the MRC S3 restore data to cbmem */ |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 271 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, |
| 272 | sizeof(*ctrl)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 273 | } |
| 274 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 275 | static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 276 | int s3_resume, int me_uma_size) |
Patrick Rudolph | 27e085a | 2016-03-26 10:59:02 +0100 | [diff] [blame] | 277 | { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 278 | if (ctrl->sandybridge) |
| 279 | return try_init_dram_ddr3_sandy(ctrl, fast_boot, s3_resume, me_uma_size); |
| 280 | else |
| 281 | return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size); |
Patrick Rudolph | 27e085a | 2016-03-26 10:59:02 +0100 | [diff] [blame] | 282 | } |
| 283 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 284 | static void init_dram_ddr3(int min_tck, int s3resume) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 285 | { |
| 286 | int me_uma_size; |
| 287 | int cbmem_was_inited; |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 288 | ramctr_timing ctrl; |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 289 | int fast_boot; |
Kyösti Mälkki | 4cb44e5 | 2016-11-18 19:11:24 +0200 | [diff] [blame] | 290 | spd_raw_data spds[4]; |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 291 | struct region_device rdev; |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 292 | ramctr_timing *ctrl_cached; |
Patrick Rudolph | 31d1959 | 2016-03-26 12:22:34 +0100 | [diff] [blame] | 293 | int err; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 294 | u32 cpu; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 295 | |
| 296 | MCHBAR32(0x5f00) |= 1; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 297 | |
| 298 | /* Wait for ME to be ready */ |
| 299 | intel_early_me_init(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 300 | me_uma_size = intel_early_me_uma_size(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 301 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 302 | printk(BIOS_DEBUG, "Starting native Platform init\n"); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 303 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 304 | u32 reg_5d10; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 305 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 306 | wait_txt_clear(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 307 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 308 | wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 309 | |
Felix Held | 55823c3 | 2018-07-28 00:41:57 +0200 | [diff] [blame] | 310 | reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000 |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 311 | if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 312 | && reg_5d10 && !s3resume) { |
Felix Held | 55823c3 | 2018-07-28 00:41:57 +0200 | [diff] [blame] | 313 | MCHBAR32(0x5d10) = 0; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 314 | /* Need reset. */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 315 | system_reset(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 316 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 317 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 318 | early_pch_init_native(); |
Patrick Rudolph | 6aca7e6 | 2019-03-26 18:22:36 +0100 | [diff] [blame] | 319 | early_init_dmi(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 320 | early_thermal_init(); |
| 321 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 322 | /* try to find timings in MRC cache */ |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 323 | int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, |
| 324 | MRC_CACHE_VERSION, &rdev); |
| 325 | if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) { |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 326 | if (s3resume) { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 327 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 328 | system_reset(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 329 | } |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 330 | ctrl_cached = NULL; |
Patrick Rudolph | 27e085a | 2016-03-26 10:59:02 +0100 | [diff] [blame] | 331 | } else { |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 332 | ctrl_cached = rdev_mmap_full(&rdev); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 333 | } |
| 334 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 335 | /* verify MRC cache for fast boot */ |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 336 | if (!s3resume && ctrl_cached) { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 337 | /* Load SPD unique information data. */ |
| 338 | memset(spds, 0, sizeof(spds)); |
| 339 | mainboard_get_spd(spds, 1); |
| 340 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 341 | /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ |
| 342 | fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); |
| 343 | if (!fast_boot) |
| 344 | printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 345 | } else { |
| 346 | fast_boot = s3resume; |
| 347 | } |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 348 | |
| 349 | if (fast_boot) { |
| 350 | printk(BIOS_DEBUG, "Trying stored timings.\n"); |
| 351 | memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); |
| 352 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 353 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 354 | if (err) { |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 355 | if (s3resume) { |
| 356 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 357 | system_reset(); |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 358 | } |
| 359 | /* no need to erase bad mrc cache here, it gets overwritten on |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 360 | * successful boot. */ |
| 361 | printk(BIOS_ERR, "Stored timings are invalid !\n"); |
| 362 | fast_boot = 0; |
| 363 | } |
| 364 | } |
| 365 | if (!fast_boot) { |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 366 | /* Reset internal state */ |
| 367 | memset(&ctrl, 0, sizeof(ctrl)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 368 | ctrl.tCK = min_tck; |
| 369 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 370 | /* Get architecture */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 371 | cpu = cpu_get_cpuid(); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 372 | ctrl.sandybridge = IS_SANDY_CPU(cpu); |
| 373 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 374 | /* Get DDR3 SPD data */ |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 375 | memset(spds, 0, sizeof(spds)); |
| 376 | mainboard_get_spd(spds, 0); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 377 | dram_find_spds_ddr3(spds, &ctrl); |
| 378 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 379 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 380 | } |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 381 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 382 | if (err) { |
| 383 | /* fallback: disable failing channel */ |
| 384 | printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); |
| 385 | printram("Disable failing channel.\n"); |
| 386 | |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 387 | /* Reset internal state */ |
| 388 | memset(&ctrl, 0, sizeof(ctrl)); |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 389 | ctrl.tCK = min_tck; |
| 390 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 391 | /* Get architecture */ |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 392 | cpu = cpu_get_cpuid(); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 393 | ctrl.sandybridge = IS_SANDY_CPU(cpu); |
| 394 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 395 | /* Reset DDR3 frequency */ |
| 396 | dram_find_spds_ddr3(spds, &ctrl); |
| 397 | |
| 398 | /* disable failing channel */ |
| 399 | disable_channel(&ctrl, GET_ERR_CHANNEL(err)); |
| 400 | |
| 401 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
| 402 | } |
| 403 | |
Patrick Rudolph | 31d1959 | 2016-03-26 12:22:34 +0100 | [diff] [blame] | 404 | if (err) |
| 405 | die("raminit failed"); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 406 | |
| 407 | /* FIXME: should be hardware revision-dependent. */ |
Felix Held | 55823c3 | 2018-07-28 00:41:57 +0200 | [diff] [blame] | 408 | MCHBAR32(0x5024) = 0x00a030ce; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 409 | |
| 410 | set_scrambling_seed(&ctrl); |
| 411 | |
| 412 | set_42a0(&ctrl); |
| 413 | |
| 414 | final_registers(&ctrl); |
| 415 | |
| 416 | /* Zone config */ |
| 417 | dram_zones(&ctrl, 0); |
| 418 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 419 | intel_early_me_status(); |
| 420 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 421 | intel_early_me_status(); |
| 422 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 423 | report_memory_config(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 424 | |
| 425 | cbmem_was_inited = !cbmem_recovery(s3resume); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 426 | if (!fast_boot) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 427 | save_timings(&ctrl); |
| 428 | if (s3resume && !cbmem_was_inited) { |
| 429 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 430 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 431 | } |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 432 | |
Nico Huber | 9ce5974 | 2018-09-13 10:52:44 +0200 | [diff] [blame] | 433 | if (!s3resume) |
| 434 | fill_smbios17(&ctrl); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 435 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 436 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 437 | void perform_raminit(int s3resume) |
| 438 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 439 | post_code(0x3a); |
| 440 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 441 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 442 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 443 | init_dram_ddr3(get_mem_min_tck(), s3resume); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 444 | } |