intel sandy/ivy: Move SPD loading after TS_BEFORE_INITRAM
Take the timestamp before SPD loading takes place, for easier
comparison against MRC blob performance and followup changes
will optimize some of the slow SPD/SMBus operations.
Change-Id: I50b5a9d02d2caf4c63e1a4025544131a085b8fb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17489
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 6ae253d..c01bc25 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -4180,13 +4180,13 @@
return 0;
}
-void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck,
- int s3resume)
+static void init_dram_ddr3(int mobile, int min_tck, int s3resume)
{
int me_uma_size;
int cbmem_was_inited;
ramctr_timing ctrl;
int fast_boot;
+ spd_raw_data spds[4];
struct mrc_data_container *mrc_cache;
ramctr_timing *ctrl_cached;
int err;
@@ -4235,6 +4235,9 @@
ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data;
}
+ memset(spds, 0, sizeof(spds));
+ mainboard_get_spd(spds);
+
/* verify MRC cache for fast boot */
if (ctrl_cached) {
/* check SPD CRC16 to make sure the DIMMs haven't been replaced */
@@ -4412,14 +4415,9 @@
void perform_raminit(int s3resume)
{
- spd_raw_data spd[4];
-
post_code(0x3a);
- memset (spd, 0, sizeof(spd));
- mainboard_get_spd(spd);
-
timestamp_add_now(TS_BEFORE_INITRAM);
- init_dram_ddr3(spd, 1, get_mem_min_tck(), s3resume);
+ init_dram_ddr3(1, get_mem_min_tck(), s3resume);
}