commit 708cf4b34e22408a673727ba04ff1264758d06c9
author Patrick Rudolph <siro@das-labor.org> Sun Jul 29 12:34:03 2018 +0200
committer Felix Held <felix-coreboot@felixheld.de> Sun Jul 29 11:09:29 2018 +0000
tree 8dcb3f23d71d1181a07d459970c55d2a2c3b6145
parent 4dc6646f5351398eeee6a944c358fcb102f75cf4

nb/intel/sandybridge: Bump MRC_CACHE_VERSION

Commit 74203de
"intel/sandybridge: Don't hardcode platform type"
changed the MRC layout.

Bump the version to prevent a boot error, if the cache isn't
cleared on flashing a new coreboot version.

Change-Id: Icd6f31bf0b30a42c66e18ab83d2434f9c3084211
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27712
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/sandybridge/raminit.c

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 47474ee..31c7d5b 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -36,7 +36,7 @@
 #include "raminit_common.h"
 #include "sandybridge.h"
 
-#define MRC_CACHE_VERSION 0
+#define MRC_CACHE_VERSION 1
 
 /* FIXME: no ECC support.  */
 /* FIXME: no support for 3-channel chipsets.  */