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review.coreboot.org / coreboot / 1a010236cf922fc28cfb36b604bdf17a9ea3cb82 / . / src / southbridge / amd / cimx / sb800 / pci_devs.h
blob: 91825ba16edd4f012f90035704ba8748e43b446c [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Mike Loptienc93a75a2014-06-06 15:16:29 -0600[diff] [blame]2
Martin Roth59338142016-01-11 12:42:35 -0700[diff] [blame]3#ifndef _CIMX_SB800_PCI_DEVS_H_
4#define _CIMX_SB800_PCI_DEVS_H_
Mike Loptienc93a75a2014-06-06 15:16:29 -0600[diff] [blame]5
Kyösti Mälkkif7ca6722017-09-10 06:30:54 +0300[diff] [blame]6#include <device/pci_def.h>
7
Elyes HAOUAS8ccc8fd2020-10-01 10:59:56 +0200[diff] [blame]8#define BUS0 0
Mike Loptienc93a75a2014-06-06 15:16:29 -0600[diff] [blame]9
10/* SATA */
Elyes HAOUAS8ccc8fd2020-10-01 10:59:56 +0200[diff] [blame]11#define SATA_DEV 0x11
12#define SATA_FUNC 0
13#define SATA_IDE_DEVID 0x4390
14#define AHCI_DEVID 0x4391
15#define RAID_DEVID 0x4392
16#define RAID5_DEVID 0x4393
17#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC)
Mike Loptienc93a75a2014-06-06 15:16:29 -0600[diff] [blame]18
19/* OHCI */
Elyes HAOUAS8ccc8fd2020-10-01 10:59:56 +0200[diff] [blame]20#define OHCI1_DEV 0x12
21#define OHCI1_FUNC 0
22#define OHCI2_DEV 0x13
23#define OHCI2_FUNC 0
24#define OHCI3_DEV 0x16
25#define OHCI3_FUNC 0
26#define OHCI4_DEV 0x14
27#define OHCI4_FUNC 5
28#define OHCI_DEVID 0x4397
29#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC)
30#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC)
31#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC)
32#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
Mike Loptienc93a75a2014-06-06 15:16:29 -0600[diff] [blame]33
34/* EHCI */
Elyes HAOUAS8ccc8fd2020-10-01 10:59:56 +0200[diff] [blame]35#define EHCI1_DEV 0x12
36#define EHCI1_FUNC 2
37#define EHCI2_DEV 0x13
38#define EHCI2_FUNC 2
39#define EHCI3_DEV 0x16
40#define EHCI3_FUNC 2
41#define EHCI_DEVID 0x4396
42#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)
43#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)
44#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
Mike Loptienc93a75a2014-06-06 15:16:29 -0600[diff] [blame]45
46/* Fusion Controller Hub */
Elyes HAOUAS8ccc8fd2020-10-01 10:59:56 +0200[diff] [blame]47#define SMBUS_DEV 0x14
48#define SMBUS_FUNC 0
49#define SMBUS_DEVID 0x4385
50#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
51
52/* IDE */
53#define IDE_DEV 0x14
54#define IDE_FUNC 1
55#define IDE_DEVID 0x439C
56#define IDE_DEVFN PCI_DEVFN(IDE_DEV, IDE_FUNC)
57
58/* HD Audio */
59#define HDA_DEV 0x14
60#define HDA_FUNC 2
61#define HDA_DEVID 0x4383
62#define HDA_DEVFN PCI_DEVFN(HDA_DEV, HDA_FUNC)
63
64/* LPC BUS */
65#define PCU_DEV 0x14
66#define LPC_DEV PCU_DEV
67#define LPC_FUNC 3
68#define LPC_DEVID 0x439D
69#define LPC_DEVFN PCI_DEVFN(LPC_DEV, LPC_FUNC)
70
71/* PCI Ports */
72#define SB_PCI_PORT_DEV 0x14
73#define SB_PCI_PORT_FUNC 4
74#define SB_PCI_PORT_DEVID 0x4384
75#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC)
76
77/* PCIe Ports */
78#define SB_PCIE_DEV 0x15
79#define SB_PCIE_PORT1_FUNC 0
80#define SB_PCIE_PORT2_FUNC 1
81#define SB_PCIE_PORT3_FUNC 2
82#define SB_PCIE_PORT4_FUNC 3
83#define SB_PCIE_PORT1_DEVID 0x43A0
84#define SB_PCIE_PORT2_DEVID 0x43A1
85#define SB_PCIE_PORT3_DEVID 0x43A2
86#define SB_PCIE_PORT4_DEVID 0x43A3
87#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC)
88#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC)
89#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC)
90#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC)
Mike Loptienc93a75a2014-06-06 15:16:29 -0600[diff] [blame]91
92#endif /* _CIMX_SB800_PCI_DEVS_H_ */