blob: 1ecff314b49d14b04d00ca4d62b746174fee9d6d [file] [log] [blame]
Mike Loptienc93a75a2014-06-06 15:16:29 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Sage Electronic Engineering, LLC.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#ifndef _CIMX_SB00_PCI_DEVS_H_
21#define _CIMX_SB00_PCI_DEVS_H_
22
23#define BUS0 0
24
25/* SATA */
26#define SATA_DEV 0x11
27#define SATA_FUNC 0
28# define SATA_IDE_DEVID 0x4390
29# define AHCI_DEVID 0x4391
30# define RAID_DEVID 0x4392
31# define RAID5_DEVID 0x4393
32# define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC)
33
34/* OHCI */
35#define OHCI1_DEV 0x12
36#define OHCI1_FUNC 0
37#define OHCI2_DEV 0x13
38#define OHCI2_FUNC 0
39#define OHCI3_DEV 0x16
40#define OHCI3_FUNC 0
41#define OHCI4_DEV 0x14
42#define OHCI4_FUNC 5
43# define OHCI_DEVID 0x4397
44# define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC)
45# define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC)
46# define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC)
47# define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC)
48
49/* EHCI */
50#define EHCI1_DEV 0x12
51#define EHCI1_FUNC 2
52#define EHCI2_DEV 0x13
53#define EHCI2_FUNC 2
54#define EHCI3_DEV 0x16
55#define EHCI3_FUNC 2
56# define EHCI_DEVID 0x4396
57# define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
58# define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC)
59# define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC)
60
61/* IDE */
62#define IDE_DEV 0x14
63#define IDE_FUNC 1
64# define IDE_DEVID 0x439C
65# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC)
66
67/* HD Audio */
68#define HDA_DEV 0x14
69#define HDA_FUNC 2
70# define HDA_DEVID 0x4383
71# define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC)
72
73/* PCI Ports */
74#define SB_PCI_PORT_DEV 0x14
75#define SB_PCI_PORT_FUNC 4
76# define SB_PCI_PORT_DEVID 0x4384
77# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
78
79/* PCIe Ports */
80#define SB_PCIE_DEV 0x15
81#define SB_PCIE_PORT1_FUNC 0
82#define SB_PCIE_PORT2_FUNC 1
83#define SB_PCIE_PORT3_FUNC 2
84#define SB_PCIE_PORT4_FUNC 3
85# define SB_PCIE_PORT1_DEVID 0x43A0
86# define SB_PCIE_PORT2_DEVID 0x43A1
87# define SB_PCIE_PORT3_DEVID 0x43A2
88# define SB_PCIE_PORT4_DEVID 0x43A3
89# define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
90# define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
91# define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
92# define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
93
94/* Fusion Controller Hub */
95#define PCU_DEV 0x14
96#define LPC_DEV PCU_DEV
97#define LPC_FUNC 3
98#define SMBUS_DEV 0x14
99#define SMBUS_FUNC 0
100# define LPC_DEVID 0x439D
101# define SMBUS_DEVID 0x4385
102# define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC)
103# define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
104
105#endif /* _CIMX_SB800_PCI_DEVS_H_ */