| Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Mike Loptien | c93a75a | 2014-06-06 15:16:29 -0600 | [diff] [blame] | 3 | |
| Martin Roth | 5933814 | 2016-01-11 12:42:35 -0700 | [diff] [blame] | 4 | #ifndef _CIMX_SB800_PCI_DEVS_H_ |
| 5 | #define _CIMX_SB800_PCI_DEVS_H_ |
| Mike Loptien | c93a75a | 2014-06-06 15:16:29 -0600 | [diff] [blame] | 6 | |
| Kyösti Mälkki | f7ca672 | 2017-09-10 06:30:54 +0300 | [diff] [blame] | 7 | #include <device/pci_def.h> |
| 8 | |
| Mike Loptien | c93a75a | 2014-06-06 15:16:29 -0600 | [diff] [blame] | 9 | #define BUS0 0 |
| 10 | |
| 11 | /* SATA */ |
| 12 | #define SATA_DEV 0x11 |
| 13 | #define SATA_FUNC 0 |
| 14 | # define SATA_IDE_DEVID 0x4390 |
| 15 | # define AHCI_DEVID 0x4391 |
| 16 | # define RAID_DEVID 0x4392 |
| 17 | # define RAID5_DEVID 0x4393 |
| 18 | # define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) |
| 19 | |
| 20 | /* OHCI */ |
| 21 | #define OHCI1_DEV 0x12 |
| 22 | #define OHCI1_FUNC 0 |
| 23 | #define OHCI2_DEV 0x13 |
| 24 | #define OHCI2_FUNC 0 |
| 25 | #define OHCI3_DEV 0x16 |
| 26 | #define OHCI3_FUNC 0 |
| 27 | #define OHCI4_DEV 0x14 |
| 28 | #define OHCI4_FUNC 5 |
| 29 | # define OHCI_DEVID 0x4397 |
| 30 | # define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) |
| 31 | # define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) |
| 32 | # define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) |
| 33 | # define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) |
| 34 | |
| 35 | /* EHCI */ |
| 36 | #define EHCI1_DEV 0x12 |
| 37 | #define EHCI1_FUNC 2 |
| 38 | #define EHCI2_DEV 0x13 |
| 39 | #define EHCI2_FUNC 2 |
| 40 | #define EHCI3_DEV 0x16 |
| 41 | #define EHCI3_FUNC 2 |
| 42 | # define EHCI_DEVID 0x4396 |
| 43 | # define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) |
| 44 | # define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) |
| 45 | # define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) |
| 46 | |
| 47 | /* IDE */ |
| 48 | #define IDE_DEV 0x14 |
| 49 | #define IDE_FUNC 1 |
| 50 | # define IDE_DEVID 0x439C |
| 51 | # define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) |
| 52 | |
| 53 | /* HD Audio */ |
| 54 | #define HDA_DEV 0x14 |
| 55 | #define HDA_FUNC 2 |
| 56 | # define HDA_DEVID 0x4383 |
| 57 | # define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) |
| 58 | |
| 59 | /* PCI Ports */ |
| 60 | #define SB_PCI_PORT_DEV 0x14 |
| 61 | #define SB_PCI_PORT_FUNC 4 |
| 62 | # define SB_PCI_PORT_DEVID 0x4384 |
| 63 | # define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) |
| 64 | |
| 65 | /* PCIe Ports */ |
| 66 | #define SB_PCIE_DEV 0x15 |
| 67 | #define SB_PCIE_PORT1_FUNC 0 |
| 68 | #define SB_PCIE_PORT2_FUNC 1 |
| 69 | #define SB_PCIE_PORT3_FUNC 2 |
| 70 | #define SB_PCIE_PORT4_FUNC 3 |
| 71 | # define SB_PCIE_PORT1_DEVID 0x43A0 |
| 72 | # define SB_PCIE_PORT2_DEVID 0x43A1 |
| 73 | # define SB_PCIE_PORT3_DEVID 0x43A2 |
| 74 | # define SB_PCIE_PORT4_DEVID 0x43A3 |
| 75 | # define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) |
| 76 | # define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) |
| 77 | # define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) |
| 78 | # define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) |
| 79 | |
| 80 | /* Fusion Controller Hub */ |
| 81 | #define PCU_DEV 0x14 |
| 82 | #define LPC_DEV PCU_DEV |
| 83 | #define LPC_FUNC 3 |
| 84 | #define SMBUS_DEV 0x14 |
| 85 | #define SMBUS_FUNC 0 |
| 86 | # define LPC_DEVID 0x439D |
| 87 | # define SMBUS_DEVID 0x4385 |
| 88 | # define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) |
| 89 | # define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) |
| 90 | |
| 91 | #endif /* _CIMX_SB800_PCI_DEVS_H_ */ |