Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 3 | |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
| 7 | #include <device/pci_ids.h> |
| 8 | #include <device/pci_ops.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 9 | #include <option.h> |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 10 | #include <pc80/mc146818rtc.h> |
Steven J. Magnani | ef79223 | 2005-09-21 13:53:44 +0000 | [diff] [blame] | 11 | #include <pc80/isa-dma.h> |
| 12 | #include <arch/io.h> |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame] | 13 | #include <arch/ioapic.h> |
Kyösti Mälkki | 12b121c | 2019-08-18 16:33:39 +0300 | [diff] [blame] | 14 | #include "chip.h" |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 15 | #include "i82801dx.h" |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 16 | |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 17 | #define NMI_OFF 0 |
| 18 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 19 | typedef struct southbridge_intel_i82801dx_config config_t; |
| 20 | |
Kyösti Mälkki | e614353 | 2013-02-26 17:24:41 +0200 | [diff] [blame] | 21 | /** |
| 22 | * Enable ACPI I/O range. |
| 23 | * |
| 24 | * @param dev PCI device with ACPI and PM BAR's |
| 25 | */ |
| 26 | static void i82801dx_enable_acpi(struct device *dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 27 | { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 28 | /* Set ACPI base address (I/O space). */ |
| 29 | pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 30 | |
Kyösti Mälkki | e614353 | 2013-02-26 17:24:41 +0200 | [diff] [blame] | 31 | /* Enable ACPI I/O range decode and ACPI power management. */ |
| 32 | pci_write_config8(dev, ACPI_CNTL, ACPI_EN); |
| 33 | } |
| 34 | |
| 35 | /** |
| 36 | * Set miscellanous static southbridge features. |
| 37 | * |
| 38 | * @param dev PCI device with I/O APIC control registers |
| 39 | */ |
| 40 | static void i82801dx_enable_ioapic(struct device *dev) |
| 41 | { |
| 42 | u32 reg32; |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 43 | |
| 44 | reg32 = pci_read_config32(dev, GEN_CNTL); |
Kyösti Mälkki | e614353 | 2013-02-26 17:24:41 +0200 | [diff] [blame] | 45 | reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ |
| 46 | reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ |
| 47 | reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ |
| 48 | reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 49 | pci_write_config32(dev, GEN_CNTL, reg32); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 50 | printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 51 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 52 | set_ioapic_id(VIO_APIC_VADDR, 0x02); |
Kyösti Mälkki | 8351243 | 2013-06-05 07:19:31 +0300 | [diff] [blame] | 53 | |
| 54 | /* |
| 55 | * Select Boot Configuration register (0x03) and |
| 56 | * use Processor System Bus (0x01) to deliver interrupts. |
| 57 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 58 | io_apic_write(VIO_APIC_VADDR, 0x03, 0x01); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 59 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 60 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 61 | static void i82801dx_enable_serial_irqs(struct device *dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 62 | { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 63 | /* Set packet length and toggle silent mode bit. */ |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 64 | pci_write_config8(dev, SERIRQ_CNTL, |
| 65 | (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 66 | pci_write_config8(dev, SERIRQ_CNTL, |
| 67 | (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 68 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 69 | |
Elyes HAOUAS | 66faf0c | 2018-05-13 13:32:56 +0200 | [diff] [blame] | 70 | static void i82801dx_pirq_init(struct device *dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 71 | { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 72 | /* Get the chip configuration */ |
| 73 | config_t *config = dev->chip_info; |
| 74 | |
| 75 | pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); |
| 76 | pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing); |
| 77 | pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing); |
| 78 | pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing); |
| 79 | pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); |
| 80 | pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); |
| 81 | pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); |
| 82 | pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 83 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 84 | |
Elyes HAOUAS | 66faf0c | 2018-05-13 13:32:56 +0200 | [diff] [blame] | 85 | static void i82801dx_power_options(struct device *dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 86 | { |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 87 | u8 reg8; |
| 88 | u16 reg16, pmbase; |
| 89 | u32 reg32; |
| 90 | const char *state; |
| 91 | |
Nico Huber | 9faae2b | 2018-11-14 00:00:35 +0100 | [diff] [blame] | 92 | int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 93 | int nmi_option; |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 94 | |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 95 | /* Which state do we want to goto after g3 (power restored)? |
| 96 | * 0 == S0 Full On |
| 97 | * 1 == S5 Soft Off |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 98 | * |
| 99 | * If the option is not existent (Laptops), use MAINBOARD_POWER_ON. |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 100 | */ |
Varad Gautam | 06ef046 | 2015-03-11 09:54:41 +0530 | [diff] [blame] | 101 | pwr_on = MAINBOARD_POWER_ON; |
| 102 | get_option(&pwr_on, "power_on_after_fail"); |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 103 | |
| 104 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 105 | reg8 &= 0xfe; |
| 106 | switch (pwr_on) { |
| 107 | case MAINBOARD_POWER_OFF: |
| 108 | reg8 |= 1; |
| 109 | state = "off"; |
| 110 | break; |
| 111 | case MAINBOARD_POWER_ON: |
| 112 | reg8 &= ~1; |
| 113 | state = "on"; |
| 114 | break; |
| 115 | case MAINBOARD_POWER_KEEP: |
| 116 | reg8 &= ~1; |
| 117 | state = "state keep"; |
| 118 | break; |
| 119 | default: |
| 120 | state = "undefined"; |
| 121 | } |
| 122 | |
| 123 | reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */ |
| 124 | |
| 125 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
Stefan Reinauer | f0aa09b | 2010-03-23 13:23:40 +0000 | [diff] [blame] | 126 | printk(BIOS_INFO, "Set power %s after power failure.\n", state); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 127 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 128 | /* Set up NMI on errors. */ |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 129 | reg8 = inb(0x61); |
| 130 | reg8 &= 0x0f; /* Higher Nibble must be 0 */ |
| 131 | reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */ |
| 132 | // reg8 &= ~(1 << 2); /* PCI SERR# Enable */ |
| 133 | reg8 |= (1 << 2); /* PCI SERR# Disable for now */ |
| 134 | outb(reg8, 0x61); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 135 | |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 136 | reg8 = inb(0x70); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 137 | nmi_option = NMI_OFF; |
Luc Verhaegen | a9c5ea0 | 2009-06-03 14:19:33 +0000 | [diff] [blame] | 138 | get_option(&nmi_option, "nmi"); |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 139 | if (nmi_option) { |
Stefan Reinauer | f0aa09b | 2010-03-23 13:23:40 +0000 | [diff] [blame] | 140 | printk(BIOS_INFO, "NMI sources enabled.\n"); |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 141 | reg8 &= ~(1 << 7); /* Set NMI. */ |
| 142 | } else { |
Stefan Reinauer | f0aa09b | 2010-03-23 13:23:40 +0000 | [diff] [blame] | 143 | printk(BIOS_INFO, "NMI sources disabled.\n"); |
Elyes HAOUAS | 9c5d463 | 2018-04-26 22:21:21 +0200 | [diff] [blame] | 144 | reg8 |= (1 << 7); /* Disable NMI. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 145 | } |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 146 | outb(reg8, 0x70); |
| 147 | |
| 148 | /* Set SMI# rate down and enable CPU_SLP# */ |
| 149 | reg16 = pci_read_config16(dev, GEN_PMCON_1); |
| 150 | reg16 &= ~(3 << 0); // SMI# rate 1 minute |
| 151 | reg16 |= (1 << 5); // CPUSLP_EN Desktop only |
| 152 | pci_write_config16(dev, GEN_PMCON_1, reg16); |
| 153 | |
| 154 | pmbase = pci_read_config16(dev, 0x40) & 0xfffe; |
| 155 | |
| 156 | /* Set up power management block and determine sleep mode */ |
| 157 | reg32 = inl(pmbase + 0x04); // PM1_CNT |
| 158 | |
| 159 | reg32 &= ~(7 << 10); // SLP_TYP |
| 160 | reg32 |= (1 << 0); // SCI_EN |
| 161 | outl(reg32, pmbase + 0x04); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 162 | } |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 163 | |
Elyes HAOUAS | 66faf0c | 2018-05-13 13:32:56 +0200 | [diff] [blame] | 164 | static void gpio_init(struct device *dev) |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 165 | { |
| 166 | /* This should be done in romstage.c already */ |
| 167 | pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1)); |
| 168 | pci_write_config8(dev, GPIO_CNTL, 0x10); |
| 169 | } |
| 170 | |
| 171 | static void i82801dx_rtc_init(struct device *dev) |
| 172 | { |
| 173 | u8 reg8; |
| 174 | u32 reg32; |
| 175 | int rtc_failed; |
| 176 | |
| 177 | reg8 = pci_read_config8(dev, GEN_PMCON_3); |
| 178 | rtc_failed = reg8 & RTC_BATTERY_DEAD; |
| 179 | if (rtc_failed) { |
| 180 | reg8 &= ~(1 << 1); /* Preserve the power fail state. */ |
| 181 | pci_write_config8(dev, GEN_PMCON_3, reg8); |
| 182 | } |
| 183 | reg32 = pci_read_config32(dev, GEN_STS); |
| 184 | rtc_failed |= reg32 & (1 << 2); |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 185 | cmos_init(rtc_failed); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 186 | |
| 187 | /* Enable access to the upper 128 byte bank of CMOS RAM. */ |
| 188 | pci_write_config8(dev, RTC_CONF, 0x04); |
| 189 | } |
| 190 | |
| 191 | static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) |
| 192 | { |
| 193 | u16 reg16; |
| 194 | int i; |
| 195 | |
| 196 | reg16 = pci_read_config16(dev, PCI_DMA_CFG); |
| 197 | reg16 &= 0x300; |
| 198 | for (i = 0; i < 8; i++) { |
| 199 | if (i == 4) |
| 200 | continue; |
| 201 | reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2); |
| 202 | } |
| 203 | pci_write_config16(dev, PCI_DMA_CFG, reg16); |
| 204 | } |
| 205 | |
Elyes HAOUAS | 66faf0c | 2018-05-13 13:32:56 +0200 | [diff] [blame] | 206 | static void i82801dx_lpc_decode_en(struct device *dev) |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 207 | { |
| 208 | /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB. |
| 209 | * LPT decode defaults to 0x378-0x37F and 0x778-0x77F. |
| 210 | * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7. |
| 211 | * We also need to set the value for LPC I/F Enables Register. |
| 212 | */ |
| 213 | pci_write_config8(dev, COM_DEC, 0x10); |
| 214 | pci_write_config16(dev, LPC_EN, 0x300F); |
| 215 | } |
| 216 | |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 217 | /* ICH4 does not mention HPET in the docs, but |
| 218 | * all ICH3 and ICH4 do have HPETs built in. |
| 219 | */ |
| 220 | static void enable_hpet(struct device *dev) |
| 221 | { |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 222 | u32 reg32, hpet, val; |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 223 | |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 224 | /* Set HPET base address and enable it */ |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 225 | printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS); |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 226 | reg32 = pci_read_config32(dev, GEN_CNTL); |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 227 | /* |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 228 | * Bit 17 is HPET enable bit. |
| 229 | * Bit 16:15 control the HPET base address. |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 230 | */ |
| 231 | reg32 &= ~(3 << 15); /* Clear it */ |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 232 | |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 233 | hpet = CONFIG_HPET_ADDRESS >> 12; |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 234 | hpet &= 0x3; |
| 235 | |
| 236 | reg32 |= (hpet << 15); |
| 237 | reg32 |= (1 << 17); /* Enable HPET. */ |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 238 | pci_write_config32(dev, GEN_CNTL, reg32); |
| 239 | |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 240 | /* Check to see whether it took */ |
| 241 | reg32 = pci_read_config32(dev, GEN_CNTL); |
| 242 | val = reg32 >> 15; |
| 243 | val &= 0x7; |
| 244 | |
| 245 | if ((val & 0x4) && (hpet == (val & 0x3))) { |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 246 | printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS); |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 247 | } else { |
Stefan Reinauer | f0aa09b | 2010-03-23 13:23:40 +0000 | [diff] [blame] | 248 | printk(BIOS_WARNING, "HPET was not enabled correctly\n"); |
Joseph Smith | b5466b0 | 2010-03-22 23:10:53 +0000 | [diff] [blame] | 249 | reg32 &= ~(1 << 17); /* Clear Enable */ |
| 250 | pci_write_config32(dev, GEN_CNTL, reg32); |
| 251 | } |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 252 | } |
| 253 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 254 | static void lpc_init(struct device *dev) |
| 255 | { |
| 256 | /* Set the value for PCI command register. */ |
| 257 | pci_write_config16(dev, PCI_COMMAND, 0x000f); |
| 258 | |
Kyösti Mälkki | e614353 | 2013-02-26 17:24:41 +0200 | [diff] [blame] | 259 | i82801dx_enable_acpi(dev); |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 260 | /* IO APIC initialization. */ |
| 261 | i82801dx_enable_ioapic(dev); |
| 262 | |
| 263 | i82801dx_enable_serial_irqs(dev); |
| 264 | |
| 265 | /* Setup the PIRQ. */ |
| 266 | i82801dx_pirq_init(dev); |
| 267 | |
| 268 | /* Setup power options. */ |
| 269 | i82801dx_power_options(dev); |
| 270 | |
| 271 | /* Set the state of the GPIO lines. */ |
| 272 | gpio_init(dev); |
| 273 | |
| 274 | /* Initialize the real time clock. */ |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 275 | i82801dx_rtc_init(dev); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 276 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 277 | /* Route DMA. */ |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 278 | i82801dx_lpc_route_dma(dev, 0xff); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 279 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 280 | /* Initialize ISA DMA. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 281 | isa_dma_init(); |
| 282 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 283 | /* Setup decode ports and LPC I/F enables. */ |
| 284 | i82801dx_lpc_decode_en(dev); |
Stefan Reinauer | 527aedc | 2010-03-17 22:08:51 +0000 | [diff] [blame] | 285 | |
| 286 | /* Initialize the High Precision Event Timers */ |
| 287 | enable_hpet(dev); |
Kyösti Mälkki | 55b7263 | 2019-07-08 22:36:38 +0300 | [diff] [blame] | 288 | |
| 289 | /* Don't allow evil boot loaders, kernels, or |
| 290 | * userspace applications to deceive us: |
| 291 | */ |
Kyösti Mälkki | cd0b67b | 2019-10-09 07:52:40 +0300 | [diff] [blame] | 292 | if (CONFIG(HAVE_SMI_HANDLER) && !CONFIG(PARALLEL_MP)) |
Kyösti Mälkki | 55b7263 | 2019-07-08 22:36:38 +0300 | [diff] [blame] | 293 | aseg_smm_lock(); |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 294 | } |
| 295 | |
Elyes HAOUAS | 66faf0c | 2018-05-13 13:32:56 +0200 | [diff] [blame] | 296 | static void i82801dx_lpc_read_resources(struct device *dev) |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 297 | { |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 298 | struct resource *res; |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 299 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 300 | /* Get the normal PCI resources of this device. */ |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 301 | pci_dev_read_resources(dev); |
| 302 | |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 303 | /* Add an extra subtractive resource for both memory and I/O. */ |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 304 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 305 | res->base = 0; |
| 306 | res->size = 0x1000; |
| 307 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 308 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 309 | |
| 310 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 311 | res->base = 0xff800000; |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 312 | res->size = 0x00800000; /* 8 MB for flash */ |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 313 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 314 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 315 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 316 | res = new_resource(dev, 3); /* IOAPIC */ |
Uwe Hermann | 74d1a6e | 2010-10-12 17:34:08 +0000 | [diff] [blame] | 317 | res->base = IO_APIC_ADDR; |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 318 | res->size = 0x00001000; |
| 319 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Eric Biederman | 4f9265f | 2004-10-22 02:33:51 +0000 | [diff] [blame] | 320 | } |
| 321 | |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 322 | static struct device_operations lpc_ops = { |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 323 | .read_resources = i82801dx_lpc_read_resources, |
| 324 | .set_resources = pci_dev_set_resources, |
Myles Watson | 7eac445 | 2010-06-17 16:16:56 +0000 | [diff] [blame] | 325 | .enable_resources = pci_dev_enable_resources, |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 326 | .init = lpc_init, |
Nico Huber | 51b75ae | 2019-03-14 16:02:05 +0100 | [diff] [blame] | 327 | .scan_bus = scan_static_bus, |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame] | 328 | .enable = i82801dx_enable, |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 329 | }; |
| 330 | |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 331 | /* 82801DB/DBL */ |
| 332 | static const struct pci_driver lpc_driver_db __pci_driver = { |
| 333 | .ops = &lpc_ops, |
| 334 | .vendor = PCI_VENDOR_ID_INTEL, |
| 335 | .device = PCI_DEVICE_ID_INTEL_82801DB_LPC, |
| 336 | }; |
| 337 | |
| 338 | /* 82801DBM */ |
| 339 | static const struct pci_driver lpc_driver_dbm __pci_driver = { |
| 340 | .ops = &lpc_ops, |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 341 | .vendor = PCI_VENDOR_ID_INTEL, |
Uwe Hermann | a29ec06 | 2007-11-04 03:21:37 +0000 | [diff] [blame] | 342 | .device = PCI_DEVICE_ID_INTEL_82801DBM_LPC, |
Ronald G. Minnich | 182615d | 2004-08-24 16:20:46 +0000 | [diff] [blame] | 343 | }; |