hpet: common ACPI generation
HPET's min ticks (minimum time between events to avoid
losing interrupts) is chipset specific, so move it to
Kconfig.
Via also has a special base address, so move it as well.
Apart from these (and the base address was already #defined),
the table is very uniform.
Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index 768e700..fbf8e12 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -233,7 +233,7 @@
u32 reg32, hpet, val;
/* Set HPET base address and enable it */
- printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", HPET_ADDR);
+ printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS);
reg32 = pci_read_config32(dev, GEN_CNTL);
/*
* Bit 17 is HPET enable bit.
@@ -241,7 +241,7 @@
*/
reg32 &= ~(3 << 15); /* Clear it */
- hpet = HPET_ADDR >> 12;
+ hpet = CONFIG_HPET_ADDRESS >> 12;
hpet &= 0x3;
reg32 |= (hpet << 15);
@@ -254,7 +254,7 @@
val &= 0x7;
if ((val & 0x4) && (hpet == (val & 0x3))) {
- printk(BIOS_INFO, "HPET enabled at 0x%x\n", HPET_ADDR);
+ printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS);
} else {
printk(BIOS_WARNING, "HPET was not enabled correctly\n");
reg32 &= ~(1 << 17); /* Clear Enable */