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review.coreboot.org / coreboot / 8670e829a8f2f6e56c2405333a171c2bc7cd017b / . / src / southbridge / amd / pi / hudson / pci_devs.h
blob: 7069fef55cf0f7a5d7ef58f770892894d5dc35de [file] [log] [blame]
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]13 */
14
15#ifndef _PI_HUDSON_PCI_DEVS_H_
16#define _PI_HUDSON_PCI_DEVS_H_
17
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]18#define BUS0 0
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]19
20/* XHCI */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]21#define XHCI_DEV 0x10
22#define XHCI_FUNC 0
23#define XHCI_DEVID 0x7814
24#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]25
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]26#define XHCI2_DEV 0x10
27#define XHCI2_FUNC 1
28#define XHCI2_DEVID 0x7814
29#define XHCI2_DEVFN PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]30
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]31/* SATA */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]32#define SATA_DEV 0x11
33#define SATA_FUNC 0
34#define SATA_IDE_DEVID 0x7800
35#define AHCI_DEVID_MS 0x7801
36#define AHCI_DEVID_AMD 0x7804
37#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]38
39/* OHCI */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]40#define OHCI1_DEV 0x12
41#define OHCI1_FUNC 0
42#define OHCI2_DEV 0x13
43#define OHCI2_FUNC 0
44#define OHCI3_DEV 0x16
45#define OHCI3_FUNC 0
46#define OHCI4_DEV 0x14
47#define OHCI4_FUNC 5
48#define OHCI_DEVID 0x7807
49#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC)
50#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC)
51#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC)
52#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]53
54/* EHCI */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]55#define EHCI1_DEV 0x12
56#define EHCI1_FUNC 2
57#define EHCI2_DEV 0x13
58#define EHCI2_FUNC 2
59#define EHCI3_DEV 0x16
60#define EHCI3_FUNC 2
61#define EHCI_DEVID 0x7808
62#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
63#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC)
64#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]65
66/* SMBUS */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]67#define SMBUS_DEV 0x14
68#define SMBUS_FUNC 0
69#define SMBUS_DEVID 0x780B
70#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]71
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]72/* IDE */
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]73#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]74#define IDE_DEV 0x14
75#define IDE_FUNC 1
76#define IDE_DEVID 0x780C
77#define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC)
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]78#endif
79
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]80/* HD Audio */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]81#define HDA_DEV 0x14
82#define HDA_FUNC 2
83#define HDA_DEVID 0x780D
84#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]85
86/* LPC BUS */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]87#define PCU_DEV 0x14
Philipp Deppenwiese30670122017-03-01 02:24:33 +0100[diff] [blame]88#define LPC_DEV PCU_DEV
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]89#define LPC_FUNC 3
90#define LPC_DEVID 0x780E
91#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]92
93/* PCI Ports */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]94#define SB_PCI_PORT_DEV 0x14
95#define SB_PCI_PORT_FUNC 4
96#define SB_PCI_PORT_DEVID 0x780F
97#define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]98
99/* SD Controller */
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]100#define SD_DEV 0x14
101#define SD_FUNC 7
102#define SD_DEVID 0x7806
103#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]104
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]105/* PCIe Ports */
Julius Wernercd49cce2019-03-05 16:53:33 -0800[diff] [blame]106#if CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON)
Marshall Dawsonc1f32332017-04-21 13:54:08 -0600[diff] [blame]107#define SB_PCIE_DEV 0x15
108#define SB_PCIE_PORT1_FUNC 0
109#define SB_PCIE_PORT2_FUNC 1
110#define SB_PCIE_PORT3_FUNC 2
111#define SB_PCIE_PORT4_FUNC 3
112#define SB_PCIE_PORT1_DEVID 0x7820
113#define SB_PCIE_PORT2_DEVID 0x7821
114#define SB_PCIE_PORT3_DEVID 0x7822
115#define SB_PCIE_PORT4_DEVID 0x7823
116#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
117#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
118#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
119#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
Dave Frodin9cfa7422015-01-27 07:19:48 -0700[diff] [blame]120#endif
121
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]122#endif /* _PI_HUDSON_PCI_DEVS_H_ */