Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 4 | * Copyright (C) 2014 Damien Zammit <damien@zamaudio.com> |
| 5 | * Copyright (C) 2014 Vladimir Serbinenko <phcoder@gmail.com> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 6 | * Copyright (C) 2016 Patrick Rudolph <siro@das-labor.org> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
Kyösti Mälkki | 1d7541f | 2014-02-17 21:34:42 +0200 | [diff] [blame] | 19 | #include <console/usb.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 20 | #include <commonlib/region.h> |
Kyösti Mälkki | 5687fc9 | 2013-11-28 18:11:49 +0200 | [diff] [blame] | 21 | #include <bootmode.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 22 | #include <string.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 23 | #include <arch/io.h> |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 24 | #include <cbmem.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 25 | #include <halt.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 26 | #include <timestamp.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 27 | #include <mrc_cache.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 28 | #include <southbridge/intel/bd82x6x/me.h> |
Arthur Heymans | 16fe790 | 2017-04-12 17:01:31 +0200 | [diff] [blame] | 29 | #include <southbridge/intel/common/smbus.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 30 | #include <cpu/x86/msr.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 31 | #include <delay.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 32 | #include <smbios.h> |
| 33 | #include <memory_info.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 34 | #include <lib.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 35 | #include "raminit_native.h" |
| 36 | #include "raminit_common.h" |
| 37 | #include "sandybridge.h" |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 38 | |
Patrick Rudolph | 708cf4b | 2018-07-29 12:34:03 +0200 | [diff] [blame] | 39 | #define MRC_CACHE_VERSION 1 |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 40 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 41 | /* FIXME: no ECC support. */ |
| 42 | /* FIXME: no support for 3-channel chipsets. */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 43 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 44 | static const char *ecc_decoder[] = { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 45 | "inactive", |
| 46 | "active on IO", |
| 47 | "disabled on IO", |
| 48 | "active" |
| 49 | }; |
| 50 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 51 | static void wait_txt_clear(void) |
| 52 | { |
| 53 | struct cpuid_result cp; |
| 54 | |
| 55 | cp = cpuid_ext(0x1, 0x0); |
| 56 | /* Check if TXT is supported? */ |
| 57 | if (!(cp.ecx & 0x40)) |
| 58 | return; |
| 59 | /* Some TXT public bit. */ |
| 60 | if (!(read32((void *)0xfed30010) & 1)) |
| 61 | return; |
| 62 | /* Wait for TXT clear. */ |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 63 | while (!(read8((void *)0xfed40000) & (1 << 7))); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 64 | } |
| 65 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 66 | /* |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 67 | * Disable a channel in ramctr_timing. |
| 68 | */ |
| 69 | static void disable_channel(ramctr_timing *ctrl, int channel) { |
| 70 | ctrl->rankmap[channel] = 0; |
| 71 | memset(&ctrl->rank_mirror[channel][0], 0, sizeof(ctrl->rank_mirror[0])); |
| 72 | ctrl->channel_size_mb[channel] = 0; |
| 73 | ctrl->cmd_stretch[channel] = 0; |
| 74 | ctrl->mad_dimm[channel] = 0; |
| 75 | memset(&ctrl->timings[channel][0], 0, sizeof(ctrl->timings[0])); |
Patrick Rudolph | 74163d6 | 2016-11-17 20:02:43 +0100 | [diff] [blame] | 76 | memset(&ctrl->info.dimm[channel][0], 0, sizeof(ctrl->info.dimm[0])); |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 77 | } |
| 78 | |
| 79 | /* |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 80 | * Fill cbmem with information for SMBIOS type 17. |
| 81 | */ |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 82 | static void fill_smbios17(ramctr_timing *ctrl) |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 83 | { |
| 84 | struct memory_info *mem_info; |
| 85 | int channel, slot; |
| 86 | struct dimm_info *dimm; |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 87 | uint16_t ddr_freq; |
| 88 | dimm_info *info = &ctrl->info; |
| 89 | |
| 90 | ddr_freq = (1000 << 8) / ctrl->tCK; |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 91 | |
| 92 | /* |
| 93 | * Allocate CBMEM area for DIMM information used to populate SMBIOS |
| 94 | * table 17 |
| 95 | */ |
| 96 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 97 | printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); |
| 98 | if (!mem_info) |
| 99 | return; |
| 100 | |
| 101 | memset(mem_info, 0, sizeof(*mem_info)); |
| 102 | |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 103 | FOR_ALL_CHANNELS for (slot = 0; slot < NUM_SLOTS; slot++) { |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 104 | dimm = &mem_info->dimm[mem_info->dimm_cnt]; |
| 105 | if (info->dimm[channel][slot].size_mb) { |
| 106 | dimm->ddr_type = MEMORY_TYPE_DDR3; |
| 107 | dimm->ddr_frequency = ddr_freq; |
| 108 | dimm->dimm_size = info->dimm[channel][slot].size_mb; |
| 109 | dimm->channel_num = channel; |
| 110 | dimm->rank_per_dimm = info->dimm[channel][slot].ranks; |
| 111 | dimm->dimm_num = slot; |
| 112 | memcpy(dimm->module_part_number, |
| 113 | info->dimm[channel][slot].part_number, 16); |
| 114 | dimm->mod_id = info->dimm[channel][slot].manufacturer_id; |
| 115 | dimm->mod_type = info->dimm[channel][slot].dimm_type; |
Patrick Rudolph | 5af2dea | 2017-10-31 11:53:13 +0100 | [diff] [blame] | 116 | dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only |
Patrick Rudolph | 15e6469 | 2018-08-17 15:24:56 +0200 | [diff] [blame^] | 117 | |
| 118 | memcpy(dimm->serial, info->dimm[channel][slot].serial, |
| 119 | MIN(sizeof(dimm->serial), |
| 120 | sizeof(info->dimm[channel][slot].serial))); |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 121 | mem_info->dimm_cnt++; |
| 122 | } |
| 123 | } |
| 124 | } |
| 125 | |
| 126 | /* |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 127 | * Dump in the log memory controller configuration as read from the memory |
| 128 | * controller registers. |
| 129 | */ |
| 130 | static void report_memory_config(void) |
| 131 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 132 | u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; |
Patrick Rudolph | 6ab7e5e | 2017-05-31 18:21:59 +0200 | [diff] [blame] | 133 | int i, refclk; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 134 | |
| 135 | addr_decoder_common = MCHBAR32(0x5000); |
| 136 | addr_decode_ch[0] = MCHBAR32(0x5004); |
| 137 | addr_decode_ch[1] = MCHBAR32(0x5008); |
| 138 | |
Patrick Rudolph | 6ab7e5e | 2017-05-31 18:21:59 +0200 | [diff] [blame] | 139 | refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; |
| 140 | |
| 141 | printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 142 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
Patrick Rudolph | 6ab7e5e | 2017-05-31 18:21:59 +0200 | [diff] [blame] | 143 | (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 144 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 145 | addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 146 | (addr_decoder_common >> 4) & 3); |
| 147 | |
| 148 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 149 | u32 ch_conf = addr_decode_ch[i]; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 150 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, |
| 151 | ch_conf); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 152 | printk(BIOS_DEBUG, " ECC %s\n", |
| 153 | ecc_decoder[(ch_conf >> 24) & 3]); |
| 154 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 155 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
| 156 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 157 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
| 158 | printk(BIOS_DEBUG, " DIMMA %d MB width x%d %s rank%s\n", |
| 159 | ((ch_conf >> 0) & 0xff) * 256, |
| 160 | ((ch_conf >> 19) & 1) ? 16 : 8, |
| 161 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 162 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
| 163 | printk(BIOS_DEBUG, " DIMMB %d MB width x%d %s rank%s\n", |
| 164 | ((ch_conf >> 8) & 0xff) * 256, |
| 165 | ((ch_conf >> 20) & 1) ? 16 : 8, |
| 166 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 167 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 168 | } |
| 169 | } |
| 170 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 171 | /* |
| 172 | * Return CRC16 match for all SPDs. |
| 173 | */ |
| 174 | static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) |
| 175 | { |
| 176 | int channel, slot, spd_slot; |
| 177 | int match = 1; |
| 178 | |
| 179 | FOR_ALL_CHANNELS { |
| 180 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 181 | spd_slot = 2 * channel + slot; |
| 182 | match &= ctrl->spd_crc[channel][slot] == |
Kyösti Mälkki | fc5d85c | 2016-11-18 18:52:04 +0200 | [diff] [blame] | 183 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 184 | } |
| 185 | } |
| 186 | return match; |
| 187 | } |
| 188 | |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 189 | void read_spd(spd_raw_data * spd, u8 addr, bool id_only) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 190 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 191 | int j; |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 192 | if (id_only) { |
| 193 | for (j = 117; j < 128; j++) |
| 194 | (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j); |
| 195 | } else { |
| 196 | for (j = 0; j < 256; j++) |
| 197 | (*spd)[j] = do_smbus_read_byte(SMBUS_IO_BASE, addr, j); |
| 198 | } |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 199 | } |
| 200 | |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 201 | static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 202 | { |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 203 | int dimms = 0, dimms_on_channel; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 204 | int channel, slot, spd_slot; |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 205 | dimm_info *dimm = &ctrl->info; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 206 | |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 207 | memset (ctrl->rankmap, 0, sizeof(ctrl->rankmap)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 208 | |
| 209 | ctrl->extended_temperature_range = 1; |
| 210 | ctrl->auto_self_refresh = 1; |
| 211 | |
| 212 | FOR_ALL_CHANNELS { |
| 213 | ctrl->channel_size_mb[channel] = 0; |
| 214 | |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 215 | dimms_on_channel = 0; |
| 216 | /* count dimms on channel */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 217 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 218 | spd_slot = 2 * channel + slot; |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 219 | printk(BIOS_DEBUG, |
| 220 | "SPD probe channel%d, slot%d\n", channel, slot); |
| 221 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 222 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 223 | if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 224 | dimms_on_channel++; |
| 225 | } |
| 226 | |
| 227 | for (slot = 0; slot < NUM_SLOTS; slot++) { |
| 228 | spd_slot = 2 * channel + slot; |
Patrick Rudolph | 5a06185 | 2017-09-22 15:19:26 +0200 | [diff] [blame] | 229 | printk(BIOS_DEBUG, |
| 230 | "SPD probe channel%d, slot%d\n", channel, slot); |
| 231 | |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 232 | /* search for XMP profile */ |
| 233 | spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], |
| 234 | spd[spd_slot], |
| 235 | DDR3_XMP_PROFILE_1); |
| 236 | |
| 237 | if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
| 238 | printram("No valid XMP profile found.\n"); |
| 239 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
| 240 | } else if (dimms_on_channel > dimm->dimm[channel][slot].dimms_per_channel) { |
| 241 | printram("XMP profile supports %u DIMMs, but %u DIMMs are installed.\n", |
| 242 | dimm->dimm[channel][slot].dimms_per_channel, |
| 243 | dimms_on_channel); |
Vagiz Trakhanov | 771be48 | 2017-10-02 10:02:35 +0000 | [diff] [blame] | 244 | if (IS_ENABLED(CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS)) |
| 245 | printk(BIOS_WARNING, "XMP maximum DIMMs will be ignored.\n"); |
| 246 | else |
| 247 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
Patrick Rudolph | bd1fdc6 | 2016-01-26 08:45:21 +0100 | [diff] [blame] | 248 | } else if (dimm->dimm[channel][slot].voltage != 1500) { |
| 249 | /* TODO: support other DDR3 voltage than 1500mV */ |
| 250 | printram("XMP profile's requested %u mV is unsupported.\n", |
| 251 | dimm->dimm[channel][slot].voltage); |
| 252 | spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); |
| 253 | } |
| 254 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 255 | /* fill in CRC16 for MRC cache */ |
| 256 | ctrl->spd_crc[channel][slot] = |
Kyösti Mälkki | fc5d85c | 2016-11-18 18:52:04 +0200 | [diff] [blame] | 257 | spd_ddr3_calc_unique_crc(spd[spd_slot], sizeof(spd_raw_data)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 258 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 259 | if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { |
| 260 | // set dimm invalid |
| 261 | dimm->dimm[channel][slot].ranks = 0; |
| 262 | dimm->dimm[channel][slot].size_mb = 0; |
| 263 | continue; |
| 264 | } |
| 265 | |
| 266 | dram_print_spd_ddr3(&dimm->dimm[channel][slot]); |
| 267 | dimms++; |
| 268 | ctrl->rank_mirror[channel][slot * 2] = 0; |
| 269 | ctrl->rank_mirror[channel][slot * 2 + 1] = dimm->dimm[channel][slot].flags.pins_mirrored; |
| 270 | ctrl->channel_size_mb[channel] += dimm->dimm[channel][slot].size_mb; |
| 271 | |
| 272 | ctrl->auto_self_refresh &= dimm->dimm[channel][slot].flags.asr; |
| 273 | ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh; |
| 274 | |
| 275 | ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); |
Patrick Rudolph | a649a54 | 2016-01-17 18:32:06 +0100 | [diff] [blame] | 276 | printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", |
| 277 | channel, ctrl->rankmap[channel]); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 278 | } |
| 279 | if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc) |
| 280 | && dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) { |
| 281 | const int ref_card_offset_table[6][6] = { |
| 282 | { 0, 0, 0, 0, 2, 2, }, |
| 283 | { 0, 0, 0, 0, 2, 2, }, |
| 284 | { 0, 0, 0, 0, 2, 2, }, |
| 285 | { 0, 0, 0, 0, 1, 1, }, |
| 286 | { 2, 2, 2, 1, 0, 0, }, |
| 287 | { 2, 2, 2, 1, 0, 0, }, |
| 288 | }; |
| 289 | ctrl->ref_card_offset[channel] = ref_card_offset_table[dimm->dimm[channel][0].reference_card] |
| 290 | [dimm->dimm[channel][1].reference_card]; |
| 291 | } else |
| 292 | ctrl->ref_card_offset[channel] = 0; |
| 293 | } |
| 294 | |
| 295 | if (!dimms) |
| 296 | die("No DIMMs were found"); |
| 297 | } |
| 298 | |
Patrick Rudolph | bb9c90a | 2016-05-29 17:05:06 +0200 | [diff] [blame] | 299 | static void save_timings(ramctr_timing *ctrl) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 300 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 301 | /* Save the MRC S3 restore data to cbmem */ |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 302 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, |
| 303 | sizeof(*ctrl)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 304 | } |
| 305 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 306 | static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 307 | int s3_resume, int me_uma_size) |
Patrick Rudolph | 27e085a | 2016-03-26 10:59:02 +0100 | [diff] [blame] | 308 | { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 309 | if (ctrl->sandybridge) |
| 310 | return try_init_dram_ddr3_sandy(ctrl, fast_boot, s3_resume, me_uma_size); |
| 311 | else |
| 312 | return try_init_dram_ddr3_ivy(ctrl, fast_boot, s3_resume, me_uma_size); |
Patrick Rudolph | 27e085a | 2016-03-26 10:59:02 +0100 | [diff] [blame] | 313 | } |
| 314 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 315 | static void init_dram_ddr3(int min_tck, int s3resume) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 316 | { |
| 317 | int me_uma_size; |
| 318 | int cbmem_was_inited; |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 319 | ramctr_timing ctrl; |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 320 | int fast_boot; |
Kyösti Mälkki | 4cb44e5 | 2016-11-18 19:11:24 +0200 | [diff] [blame] | 321 | spd_raw_data spds[4]; |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 322 | struct region_device rdev; |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 323 | ramctr_timing *ctrl_cached; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 324 | struct cpuid_result cpures; |
Patrick Rudolph | 31d1959 | 2016-03-26 12:22:34 +0100 | [diff] [blame] | 325 | int err; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 326 | u32 cpu; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 327 | |
| 328 | MCHBAR32(0x5f00) |= 1; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 329 | |
| 330 | /* Wait for ME to be ready */ |
| 331 | intel_early_me_init(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 332 | me_uma_size = intel_early_me_uma_size(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 333 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 334 | printk(BIOS_DEBUG, "Starting native Platform init\n"); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 335 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 336 | u32 reg_5d10; |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 337 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 338 | wait_txt_clear(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 339 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 340 | wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 341 | |
Felix Held | 55823c3 | 2018-07-28 00:41:57 +0200 | [diff] [blame] | 342 | reg_5d10 = MCHBAR32(0x5d10); // !!! = 0x00000000 |
Kyösti Mälkki | d45114f | 2013-07-26 08:53:59 +0300 | [diff] [blame] | 343 | if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 344 | && reg_5d10 && !s3resume) { |
Felix Held | 55823c3 | 2018-07-28 00:41:57 +0200 | [diff] [blame] | 345 | MCHBAR32(0x5d10) = 0; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 346 | /* Need reset. */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 347 | outb(0x6, 0xcf9); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 348 | |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 349 | halt(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 350 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 351 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 352 | early_pch_init_native(); |
| 353 | early_thermal_init(); |
| 354 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 355 | /* try to find timings in MRC cache */ |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 356 | int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, |
| 357 | MRC_CACHE_VERSION, &rdev); |
| 358 | if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) { |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 359 | if (s3resume) { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 360 | /* Failed S3 resume, reset to come up cleanly */ |
| 361 | outb(0x6, 0xcf9); |
| 362 | halt(); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 363 | } |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 364 | ctrl_cached = NULL; |
Patrick Rudolph | 27e085a | 2016-03-26 10:59:02 +0100 | [diff] [blame] | 365 | } else { |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 366 | ctrl_cached = rdev_mmap_full(&rdev); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 367 | } |
| 368 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 369 | /* verify MRC cache for fast boot */ |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 370 | if (!s3resume && ctrl_cached) { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 371 | /* Load SPD unique information data. */ |
| 372 | memset(spds, 0, sizeof(spds)); |
| 373 | mainboard_get_spd(spds, 1); |
| 374 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 375 | /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ |
| 376 | fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); |
| 377 | if (!fast_boot) |
| 378 | printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); |
Kyösti Mälkki | 38cb822 | 2016-11-18 19:25:52 +0200 | [diff] [blame] | 379 | } else { |
| 380 | fast_boot = s3resume; |
| 381 | } |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 382 | |
| 383 | if (fast_boot) { |
| 384 | printk(BIOS_DEBUG, "Trying stored timings.\n"); |
| 385 | memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); |
| 386 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 387 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 388 | if (err) { |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 389 | if (s3resume) { |
| 390 | /* Failed S3 resume, reset to come up cleanly */ |
| 391 | outb(0x6, 0xcf9); |
| 392 | halt(); |
| 393 | } |
| 394 | /* no need to erase bad mrc cache here, it gets overwritten on |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 395 | * successful boot. */ |
| 396 | printk(BIOS_ERR, "Stored timings are invalid !\n"); |
| 397 | fast_boot = 0; |
| 398 | } |
| 399 | } |
| 400 | if (!fast_boot) { |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 401 | /* Reset internal state */ |
| 402 | memset(&ctrl, 0, sizeof(ctrl)); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 403 | ctrl.tCK = min_tck; |
| 404 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 405 | /* Get architecture */ |
| 406 | cpures = cpuid(1); |
| 407 | cpu = cpures.eax; |
| 408 | ctrl.sandybridge = IS_SANDY_CPU(cpu); |
| 409 | |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 410 | /* Get DDR3 SPD data */ |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 411 | memset(spds, 0, sizeof(spds)); |
| 412 | mainboard_get_spd(spds, 0); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 413 | dram_find_spds_ddr3(spds, &ctrl); |
| 414 | |
Patrick Rudolph | 588ccaa | 2016-04-20 18:00:27 +0200 | [diff] [blame] | 415 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 416 | } |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 417 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 418 | if (err) { |
| 419 | /* fallback: disable failing channel */ |
| 420 | printk(BIOS_ERR, "RAM training failed, trying fallback.\n"); |
| 421 | printram("Disable failing channel.\n"); |
| 422 | |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 423 | /* Reset internal state */ |
| 424 | memset(&ctrl, 0, sizeof(ctrl)); |
Patrick Rudolph | e74ad21 | 2016-11-16 18:06:50 +0100 | [diff] [blame] | 425 | ctrl.tCK = min_tck; |
| 426 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 427 | /* Get architecture */ |
| 428 | cpures = cpuid(1); |
| 429 | cpu = cpures.eax; |
| 430 | ctrl.sandybridge = IS_SANDY_CPU(cpu); |
| 431 | |
Patrick Rudolph | 2ccb74b | 2016-03-26 12:16:29 +0100 | [diff] [blame] | 432 | /* Reset DDR3 frequency */ |
| 433 | dram_find_spds_ddr3(spds, &ctrl); |
| 434 | |
| 435 | /* disable failing channel */ |
| 436 | disable_channel(&ctrl, GET_ERR_CHANNEL(err)); |
| 437 | |
| 438 | err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); |
| 439 | } |
| 440 | |
Patrick Rudolph | 31d1959 | 2016-03-26 12:22:34 +0100 | [diff] [blame] | 441 | if (err) |
| 442 | die("raminit failed"); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 443 | |
| 444 | /* FIXME: should be hardware revision-dependent. */ |
Felix Held | 55823c3 | 2018-07-28 00:41:57 +0200 | [diff] [blame] | 445 | MCHBAR32(0x5024) = 0x00a030ce; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 446 | |
| 447 | set_scrambling_seed(&ctrl); |
| 448 | |
| 449 | set_42a0(&ctrl); |
| 450 | |
| 451 | final_registers(&ctrl); |
| 452 | |
| 453 | /* Zone config */ |
| 454 | dram_zones(&ctrl, 0); |
| 455 | |
Patrick Rudolph | 77db3e1 | 2016-11-26 10:11:14 +0100 | [diff] [blame] | 456 | /* Non intrusive, fast ram check */ |
| 457 | quick_ram_check(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 458 | |
| 459 | intel_early_me_status(); |
| 460 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 461 | intel_early_me_status(); |
| 462 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 463 | report_memory_config(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 464 | |
| 465 | cbmem_was_inited = !cbmem_recovery(s3resume); |
Patrick Rudolph | 56abd4d | 2016-03-13 11:07:45 +0100 | [diff] [blame] | 466 | if (!fast_boot) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 467 | save_timings(&ctrl); |
| 468 | if (s3resume && !cbmem_was_inited) { |
| 469 | /* Failed S3 resume, reset to come up cleanly */ |
| 470 | outb(0x6, 0xcf9); |
| 471 | halt(); |
| 472 | } |
Patrick Rudolph | b97009e | 2016-02-28 15:24:04 +0100 | [diff] [blame] | 473 | |
Patrick Rudolph | 735ecce | 2016-03-26 10:42:27 +0100 | [diff] [blame] | 474 | fill_smbios17(&ctrl); |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 475 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 476 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 477 | void perform_raminit(int s3resume) |
| 478 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 479 | post_code(0x3a); |
| 480 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 481 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 482 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 483 | init_dram_ddr3(get_mem_min_tck(), s3resume); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 484 | } |