Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame^] | 17 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 19 | #include <cbmem.h> |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <device/pci_ids.h> |
| 24 | #include <reg_script.h> |
| 25 | |
| 26 | #include <soc/iomap.h> |
| 27 | #include <soc/iosf.h> |
| 28 | #include <soc/lpc.h> |
| 29 | #include <soc/nvs.h> |
| 30 | #include <soc/pattrs.h> |
| 31 | #include <soc/pci_devs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 32 | #include <soc/pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | #include <soc/ramstage.h> |
| 34 | #include "chip.h" |
| 35 | |
| 36 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 37 | /* |
| 38 | * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB |
| 39 | * address. Just take 1MiB @ 512MiB. |
| 40 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 41 | #define FIRMWARE_PHYS_BASE (512 << 20) |
Matt DeVillier | 83ef07a | 2018-01-21 16:37:24 -0600 | [diff] [blame] | 42 | #define FIRMWARE_PHYS_LENGTH (2 << 20) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 43 | #define FIRMWARE_PCI_REG_BASE 0xa8 |
| 44 | #define FIRMWARE_PCI_REG_LENGTH 0xac |
| 45 | #define FIRMWARE_REG_BASE_C0 0x144000 |
| 46 | #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) |
| 47 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 48 | static void assign_device_nvs(struct device *dev, u32 *field, |
| 49 | unsigned int index) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 50 | { |
| 51 | struct resource *res; |
| 52 | |
| 53 | res = find_resource(dev, index); |
| 54 | if (res) |
| 55 | *field = res->base; |
| 56 | } |
| 57 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 58 | static void lpe_enable_acpi_mode(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 59 | { |
| 60 | static const struct reg_script ops[] = { |
| 61 | /* Disable PCI interrupt, enable Memory and Bus Master */ |
| 62 | REG_PCI_OR32(PCI_COMMAND, |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 63 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
| 64 | | PCI_COMMAND_INT_DISABLE), |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 65 | /* Enable ACPI mode */ |
| 66 | REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, |
| 67 | LPE_PCICFGCTR1_PCI_CFG_DIS | |
| 68 | LPE_PCICFGCTR1_ACPI_INT_EN), |
| 69 | REG_SCRIPT_END |
| 70 | }; |
| 71 | global_nvs_t *gnvs; |
| 72 | |
| 73 | /* Find ACPI NVS to update BARs */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 74 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 75 | if (!gnvs) { |
| 76 | printk(BIOS_ERR, "Unable to locate Global NVS\n"); |
| 77 | return; |
| 78 | } |
| 79 | |
| 80 | /* Save BAR0, BAR1, and firmware base to ACPI NVS */ |
| 81 | assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 82 | assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 83 | assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); |
| 84 | |
| 85 | /* Device is enabled in ACPI mode */ |
| 86 | gnvs->dev.lpe_en = 1; |
| 87 | |
| 88 | /* Put device in ACPI mode */ |
| 89 | reg_script_run_on_dev(dev, ops); |
| 90 | } |
| 91 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 92 | static void setup_codec_clock(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 93 | { |
| 94 | uint32_t reg; |
| 95 | u32 *clk_reg; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 96 | struct soc_intel_braswell_config *config; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 97 | const char *freq_str; |
| 98 | |
| 99 | config = dev->chip_info; |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 100 | switch (config->lpe_codec_clk_src) { |
| 101 | case LPE_CLK_SRC_XTAL: |
| 102 | /* XTAL driven bit2=0 */ |
| 103 | freq_str = "19.2MHz External Crystal"; |
| 104 | reg = CLK_SRC_XTAL; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 105 | break; |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 106 | case LPE_CLK_SRC_PLL: |
| 107 | /* PLL driven bit2=1 */ |
| 108 | freq_str = "19.2MHz PLL"; |
| 109 | reg = CLK_SRC_PLL; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 110 | break; |
| 111 | default: |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 112 | reg = CLK_SRC_XTAL; |
| 113 | printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n"); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 114 | return; |
| 115 | } |
| 116 | |
| 117 | /* Default to always running. */ |
| 118 | reg |= CLK_CTL_ON; |
| 119 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 120 | |
| 121 | printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); |
| 122 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 123 | clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 124 | |
| 125 | write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); |
| 126 | } |
| 127 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 128 | static void lpe_stash_firmware_info(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 129 | { |
| 130 | struct resource *res; |
| 131 | struct resource *mmio; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 132 | |
| 133 | res = find_resource(dev, FIRMWARE_PCI_REG_BASE); |
| 134 | if (res == NULL) { |
| 135 | printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); |
| 136 | return; |
| 137 | } |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 138 | printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 139 | |
| 140 | /* Continue using old way of informing firmware address / size. */ |
| 141 | pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); |
| 142 | pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); |
| 143 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 144 | /* Also put the address in MMIO space like on C0 BTM */ |
| 145 | mmio = find_resource(dev, PCI_BASE_ADDRESS_0); |
Lee Leahy | d94cff6 | 2017-03-16 17:49:42 -0700 | [diff] [blame] | 146 | write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 147 | res->base); |
Lee Leahy | d94cff6 | 2017-03-16 17:49:42 -0700 | [diff] [blame] | 148 | write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 149 | res->size); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 150 | } |
| 151 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 152 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 153 | static void lpe_init(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 154 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 155 | struct soc_intel_braswell_config *config = dev->chip_info; |
| 156 | |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 157 | printk(BIOS_SPEW, "%s/%s (%s)\n", |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 158 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 159 | |
| 160 | lpe_stash_firmware_info(dev); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 161 | setup_codec_clock(dev); |
| 162 | |
| 163 | if (config->lpe_acpi_mode) |
| 164 | lpe_enable_acpi_mode(dev); |
| 165 | } |
| 166 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 167 | static void lpe_read_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 168 | { |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 169 | struct resource *res; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 170 | pci_dev_read_resources(dev); |
| 171 | |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 172 | /* |
| 173 | * Allocate the BAR1 resource at index 2 to fulfil the Windows driver |
| 174 | * interface requirements even though the PCI device has only one BAR |
| 175 | */ |
| 176 | res = new_resource(dev, PCI_BASE_ADDRESS_2); |
| 177 | res->base = 0; |
| 178 | res->size = 0x1000; |
| 179 | res->limit = 0xffffffff; |
| 180 | res->gran = 12; |
| 181 | res->align = 12; |
| 182 | res->flags = IORESOURCE_MEM; |
| 183 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 184 | reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, |
| 185 | FIRMWARE_PHYS_BASE >> 10, |
| 186 | FIRMWARE_PHYS_LENGTH >> 10); |
| 187 | } |
| 188 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 189 | static void lpe_set_resources(struct device *dev) |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 190 | { |
| 191 | struct resource *res; |
| 192 | |
| 193 | res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 194 | if (res != NULL) |
| 195 | res->flags |= IORESOURCE_STORED; |
| 196 | |
| 197 | pci_dev_set_resources(dev); |
| 198 | } |
| 199 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 200 | static const struct device_operations device_ops = { |
| 201 | .read_resources = lpe_read_resources, |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 202 | .set_resources = lpe_set_resources, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 203 | .enable_resources = pci_dev_enable_resources, |
| 204 | .init = lpe_init, |
| 205 | .enable = NULL, |
| 206 | .scan_bus = NULL, |
| 207 | .ops_pci = &soc_pci_ops, |
| 208 | }; |
| 209 | |
| 210 | static const struct pci_driver southcluster __pci_driver = { |
| 211 | .ops = &device_ops, |
| 212 | .vendor = PCI_VENDOR_ID_INTEL, |
| 213 | .device = LPE_DEVID, |
| 214 | }; |