Braswell: Add Braswell SOC support
Add the files to support the Braswell SOC.
BRANCH=none
BUG=None
TEST=Build for a Braswell platform
Change-Id: I968da68733e57647d0a08e4040ff0378b4d59004
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10051
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index fdac299..fa4b695 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -31,13 +32,15 @@
#include <soc/nvs.h>
#include <soc/pattrs.h>
#include <soc/pci_devs.h>
-#include <soc/pmc.h>
+#include <soc/pm.h>
#include <soc/ramstage.h>
#include "chip.h"
-/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
- * address. Just take 1MiB @ 512MiB. */
+/*
+ * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
+ * address. Just take 1MiB @ 512MiB.
+ */
#define FIRMWARE_PHYS_BASE (512 << 20)
#define FIRMWARE_PHYS_LENGTH (1 << 20)
#define FIRMWARE_PCI_REG_BASE 0xa8
@@ -59,7 +62,8 @@
static const struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR32(PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
+ | PCI_COMMAND_INT_DISABLE),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
LPE_PCICFGCTR1_PCI_CFG_DIS |
@@ -69,7 +73,7 @@
global_nvs_t *gnvs;
/* Find ACPI NVS to update BARs */
- gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS);
+ gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
printk(BIOS_ERR, "Unable to locate Global NVS\n");
return;
@@ -77,7 +81,8 @@
/* Save BAR0, BAR1, and firmware base to ACPI NVS */
assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0);
- assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1);
+ /* LPE seems does not have BAR at PCI_BASE_ADDRESS_1 so disable it. */
+ /* assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); */
assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE);
/* Device is enabled in ACPI mode */
@@ -91,7 +96,7 @@
{
uint32_t reg;
u32 *clk_reg;
- struct soc_intel_baytrail_config *config;
+ struct soc_intel_braswell_config *config;
const char *freq_str;
config = dev->chip_info;
@@ -119,7 +124,7 @@
printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
- clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
+ clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
clk_reg += config->lpe_codec_clk_num;
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
@@ -129,34 +134,35 @@
{
struct resource *res;
struct resource *mmio;
- const struct pattrs *pattrs = pattrs_get();
res = find_resource(dev, FIRMWARE_PCI_REG_BASE);
if (res == NULL) {
printk(BIOS_DEBUG, "LPE Firmware memory not found.\n");
return;
}
+ printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base);
/* Continue using old way of informing firmware address / size. */
pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);
- /* C0 and later steppings use an offset in the MMIO space. */
- if (pattrs->stepping >= STEP_C0) {
- mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
- write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0),
- res->base);
- write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0),
- res->size);
- }
+ /* Also put the address in MMIO space like on C0 BTM */
+ mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
+ write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), \
+ res->base);
+ write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), \
+ res->size);
}
+
static void lpe_init(device_t dev)
{
- struct soc_intel_baytrail_config *config = dev->chip_info;
+ struct soc_intel_braswell_config *config = dev->chip_info;
+
+ printk(BIOS_SPEW, "%s/%s ( %s )\n",
+ __FILE__, __func__, dev_name(dev));
lpe_stash_firmware_info(dev);
-
setup_codec_clock(dev);
if (config->lpe_acpi_mode)