Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <cbmem.h> |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <reg_script.h> |
| 27 | |
| 28 | #include <soc/iomap.h> |
| 29 | #include <soc/iosf.h> |
| 30 | #include <soc/lpc.h> |
| 31 | #include <soc/nvs.h> |
| 32 | #include <soc/pattrs.h> |
| 33 | #include <soc/pci_devs.h> |
| 34 | #include <soc/pmc.h> |
| 35 | #include <soc/ramstage.h> |
| 36 | #include "chip.h" |
| 37 | |
| 38 | |
| 39 | /* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB |
| 40 | * address. Just take 1MiB @ 512MiB. */ |
| 41 | #define FIRMWARE_PHYS_BASE (512 << 20) |
| 42 | #define FIRMWARE_PHYS_LENGTH (1 << 20) |
| 43 | #define FIRMWARE_PCI_REG_BASE 0xa8 |
| 44 | #define FIRMWARE_PCI_REG_LENGTH 0xac |
| 45 | #define FIRMWARE_REG_BASE_C0 0x144000 |
| 46 | #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) |
| 47 | |
| 48 | static void assign_device_nvs(device_t dev, u32 *field, unsigned index) |
| 49 | { |
| 50 | struct resource *res; |
| 51 | |
| 52 | res = find_resource(dev, index); |
| 53 | if (res) |
| 54 | *field = res->base; |
| 55 | } |
| 56 | |
| 57 | static void lpe_enable_acpi_mode(device_t dev) |
| 58 | { |
| 59 | static const struct reg_script ops[] = { |
| 60 | /* Disable PCI interrupt, enable Memory and Bus Master */ |
| 61 | REG_PCI_OR32(PCI_COMMAND, |
| 62 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), |
| 63 | /* Enable ACPI mode */ |
| 64 | REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, |
| 65 | LPE_PCICFGCTR1_PCI_CFG_DIS | |
| 66 | LPE_PCICFGCTR1_ACPI_INT_EN), |
| 67 | REG_SCRIPT_END |
| 68 | }; |
| 69 | global_nvs_t *gnvs; |
| 70 | |
| 71 | /* Find ACPI NVS to update BARs */ |
| 72 | gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 73 | if (!gnvs) { |
| 74 | printk(BIOS_ERR, "Unable to locate Global NVS\n"); |
| 75 | return; |
| 76 | } |
| 77 | |
| 78 | /* Save BAR0, BAR1, and firmware base to ACPI NVS */ |
| 79 | assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); |
| 80 | assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_1); |
| 81 | assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); |
| 82 | |
| 83 | /* Device is enabled in ACPI mode */ |
| 84 | gnvs->dev.lpe_en = 1; |
| 85 | |
| 86 | /* Put device in ACPI mode */ |
| 87 | reg_script_run_on_dev(dev, ops); |
| 88 | } |
| 89 | |
| 90 | static void setup_codec_clock(device_t dev) |
| 91 | { |
| 92 | uint32_t reg; |
| 93 | u32 *clk_reg; |
| 94 | struct soc_intel_baytrail_config *config; |
| 95 | const char *freq_str; |
| 96 | |
| 97 | config = dev->chip_info; |
| 98 | switch (config->lpe_codec_clk_freq) { |
| 99 | case 19: |
| 100 | freq_str = "19.2"; |
| 101 | reg = CLK_FREQ_19P2MHZ; |
| 102 | break; |
| 103 | case 25: |
| 104 | freq_str = "25"; |
| 105 | reg = CLK_FREQ_25MHZ; |
| 106 | break; |
| 107 | default: |
| 108 | printk(BIOS_DEBUG, "LPE codec clock not required.\n"); |
| 109 | return; |
| 110 | } |
| 111 | |
| 112 | /* Default to always running. */ |
| 113 | reg |= CLK_CTL_ON; |
| 114 | |
| 115 | if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { |
| 116 | printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); |
| 117 | return; |
| 118 | } |
| 119 | |
| 120 | printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); |
| 121 | |
| 122 | clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); |
| 123 | clk_reg += config->lpe_codec_clk_num; |
| 124 | |
| 125 | write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); |
| 126 | } |
| 127 | |
| 128 | static void lpe_stash_firmware_info(device_t dev) |
| 129 | { |
| 130 | struct resource *res; |
| 131 | struct resource *mmio; |
| 132 | const struct pattrs *pattrs = pattrs_get(); |
| 133 | |
| 134 | res = find_resource(dev, FIRMWARE_PCI_REG_BASE); |
| 135 | if (res == NULL) { |
| 136 | printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); |
| 137 | return; |
| 138 | } |
| 139 | |
| 140 | /* Continue using old way of informing firmware address / size. */ |
| 141 | pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); |
| 142 | pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); |
| 143 | |
| 144 | /* C0 and later steppings use an offset in the MMIO space. */ |
| 145 | if (pattrs->stepping >= STEP_C0) { |
| 146 | mmio = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 147 | write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), |
| 148 | res->base); |
| 149 | write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), |
| 150 | res->size); |
| 151 | } |
| 152 | } |
| 153 | |
| 154 | static void lpe_init(device_t dev) |
| 155 | { |
| 156 | struct soc_intel_baytrail_config *config = dev->chip_info; |
| 157 | |
| 158 | lpe_stash_firmware_info(dev); |
| 159 | |
| 160 | setup_codec_clock(dev); |
| 161 | |
| 162 | if (config->lpe_acpi_mode) |
| 163 | lpe_enable_acpi_mode(dev); |
| 164 | } |
| 165 | |
| 166 | static void lpe_read_resources(device_t dev) |
| 167 | { |
| 168 | pci_dev_read_resources(dev); |
| 169 | |
| 170 | reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, |
| 171 | FIRMWARE_PHYS_BASE >> 10, |
| 172 | FIRMWARE_PHYS_LENGTH >> 10); |
| 173 | } |
| 174 | |
| 175 | static const struct device_operations device_ops = { |
| 176 | .read_resources = lpe_read_resources, |
| 177 | .set_resources = pci_dev_set_resources, |
| 178 | .enable_resources = pci_dev_enable_resources, |
| 179 | .init = lpe_init, |
| 180 | .enable = NULL, |
| 181 | .scan_bus = NULL, |
| 182 | .ops_pci = &soc_pci_ops, |
| 183 | }; |
| 184 | |
| 185 | static const struct pci_driver southcluster __pci_driver = { |
| 186 | .ops = &device_ops, |
| 187 | .vendor = PCI_VENDOR_ID_INTEL, |
| 188 | .device = LPE_DEVID, |
| 189 | }; |