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Ravi Sarawadi91ffac82022-05-07 16:37:09 -07001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <device/device.h>
4#include <device/pci.h>
5#include <fsp/api.h>
6#include <fsp/util.h>
Dinesh Gehlot166c75c72023-01-03 05:26:19 +00007#include <gpio.h>
Ravi Sarawadi91ffac82022-05-07 16:37:09 -07008#include <intelblocks/acpi.h>
9#include <intelblocks/cfg.h>
Subrata Banikad42d9c2023-04-19 18:30:53 +053010#include <intelblocks/cse.h>
Kapil Porwalcca3c902022-12-19 23:57:15 +053011#include <intelblocks/irq.h>
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070012#include <intelblocks/itss.h>
John Zhao54a03e42022-08-03 20:07:03 -070013#include <intelblocks/p2sb.h>
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070014#include <intelblocks/pcie_rp.h>
15#include <intelblocks/systemagent.h>
John Zhao54a03e42022-08-03 20:07:03 -070016#include <intelblocks/tcss.h>
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070017#include <intelblocks/xdci.h>
Subrata Banik94055412023-05-17 14:33:55 +053018#include <soc/intel/common/reset.h>
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070019#include <soc/intel/common/vbt.h>
John Zhao54a03e42022-08-03 20:07:03 -070020#include <soc/iomap.h>
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070021#include <soc/itss.h>
22#include <soc/p2sb.h>
23#include <soc/pci_devs.h>
24#include <soc/pcie.h>
25#include <soc/ramstage.h>
26#include <soc/soc_chip.h>
John Zhao54a03e42022-08-03 20:07:03 -070027#include <soc/tcss.h>
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070028
29#if CONFIG(HAVE_ACPI_TABLES)
30const char *soc_acpi_name(const struct device *dev)
31{
32 if (dev->path.type == DEVICE_PATH_DOMAIN)
33 return "PCI0";
34
35 if (dev->path.type == DEVICE_PATH_USB) {
36 switch (dev->path.usb.port_type) {
37 case 0:
38 /* Root Hub */
39 return "RHUB";
40 case 2:
41 /* USB2 ports */
42 switch (dev->path.usb.port_id) {
43 case 0: return "HS01";
44 case 1: return "HS02";
45 case 2: return "HS03";
46 case 3: return "HS04";
47 case 4: return "HS05";
48 case 5: return "HS06";
49 case 6: return "HS07";
50 case 7: return "HS08";
51 case 8: return "HS09";
52 case 9: return "HS10";
53 }
54 break;
55 case 3:
56 /* USB3 ports */
57 switch (dev->path.usb.port_id) {
58 case 0: return "SS01";
59 case 1: return "SS02";
60 case 2: return "SS03";
61 case 3: return "SS04";
62 }
63 break;
64 }
65 printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.usb.port_type);
66 return NULL;
67 }
68 if (dev->path.type != DEVICE_PATH_PCI) {
69 printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.type);
70 return NULL;
71 }
72
73 switch (dev->path.pci.devfn) {
74 case PCI_DEVFN_ROOT: return "MCHC";
Won Chungede55642023-05-16 17:11:21 +000075 case PCI_DEVFN_IGD: return "GFX0";
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070076 case PCI_DEVFN_TCSS_XHCI: return "TXHC";
77 case PCI_DEVFN_TCSS_XDCI: return "TXDC";
78 case PCI_DEVFN_TCSS_DMA0: return "TDM0";
79 case PCI_DEVFN_TCSS_DMA1: return "TDM1";
80 case PCI_DEVFN_TBT0: return "TRP0";
81 case PCI_DEVFN_TBT1: return "TRP1";
82 case PCI_DEVFN_TBT2: return "TRP2";
83 case PCI_DEVFN_TBT3: return "TRP3";
84 case PCI_DEVFN_IPU: return "IPU0";
85 case PCI_DEVFN_ISH: return "ISHB";
Matt DeVillierecf2b422023-08-31 10:06:00 -050086 case PCI_DEVFN_GNA: return "GNA";
Ravi Sarawadi91ffac82022-05-07 16:37:09 -070087 case PCI_DEVFN_XHCI: return "XHCI";
88 case PCI_DEVFN_I2C0: return "I2C0";
89 case PCI_DEVFN_I2C1: return "I2C1";
90 case PCI_DEVFN_I2C2: return "I2C2";
91 case PCI_DEVFN_I2C3: return "I2C3";
92 case PCI_DEVFN_I2C4: return "I2C4";
93 case PCI_DEVFN_I2C5: return "I2C5";
94 case PCI_DEVFN_SATA: return "SATA";
95 case PCI_DEVFN_PCIE1: return "RP01";
96 case PCI_DEVFN_PCIE2: return "RP02";
97 case PCI_DEVFN_PCIE3: return "RP03";
98 case PCI_DEVFN_PCIE4: return "RP04";
99 case PCI_DEVFN_PCIE5: return "RP05";
100 case PCI_DEVFN_PCIE6: return "RP06";
101 case PCI_DEVFN_PCIE7: return "RP07";
102 case PCI_DEVFN_PCIE8: return "RP08";
103 case PCI_DEVFN_PCIE9: return "RP09";
104 case PCI_DEVFN_PCIE10: return "RP10";
105 case PCI_DEVFN_PCIE11: return "RP11";
106 case PCI_DEVFN_PCIE12: return "RP12";
107 case PCI_DEVFN_PMC: return "PMC";
108 case PCI_DEVFN_UART0: return "UAR0";
109 case PCI_DEVFN_UART1: return "UAR1";
110 case PCI_DEVFN_UART2: return "UAR2";
111 case PCI_DEVFN_GSPI0: return "SPI0";
112 case PCI_DEVFN_GSPI1: return "SPI1";
Angel Ponsc7c746c2022-07-16 12:37:38 +0200113 case PCI_DEVFN_GSPI2: return "SPI2";
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700114 /* Keeping ACPI device name coherent with ec.asl */
115 case PCI_DEVFN_ESPI: return "LPCB";
116 case PCI_DEVFN_HDA: return "HDAS";
117 case PCI_DEVFN_SMBUS: return "SBUS";
118 case PCI_DEVFN_GBE: return "GLAN";
119 }
Subrata Banike70bc422023-02-17 03:18:50 +0530120 printk(BIOS_DEBUG, "Missing ACPI Name for PCI: 00:%02x.%01x\n",
121 PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn));
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700122 return NULL;
123}
124#endif
125
Subrata Banik59302632023-08-13 19:44:53 +0000126#if CONFIG(SOC_INTEL_STORE_ISH_FW_VERSION)
127/* SoC override API to identify if ISH Firmware existed inside CSE FPT */
128bool soc_is_ish_partition_enabled(void)
129{
130 struct device *ish = pcidev_path_on_root(PCI_DEVFN_ISH);
131 uint16_t ish_pci_id = ish ? pci_read_config16(ish, PCI_DEVICE_ID) : 0xFFFF;
132
133 if (ish_pci_id == 0xFFFF)
134 return false;
135
136 return true;
137}
138#endif
139
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700140/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
141static void soc_fill_gpio_pm_configuration(void)
142{
143 uint8_t value[TOTAL_GPIO_COMM];
144 const config_t *config = config_of_soc();
145
146 if (config->gpio_override_pm)
147 memcpy(value, config->gpio_pm, sizeof(value));
148 else
149 memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value));
150
151 gpio_pm_configure(value, TOTAL_GPIO_COMM);
152}
153
154void soc_init_pre_device(void *chip_info)
155{
John Zhao54a03e42022-08-03 20:07:03 -0700156 config_t *config = config_of_soc();
157
158 /* Validate TBT image authentication */
159 config->tbt_authentication = ioe_p2sb_sbi_read(PID_IOM,
160 IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
161
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700162 /* Perform silicon specific init. */
163 fsp_silicon_init();
164
165 /* Display FIRMWARE_VERSION_INFO_HOB */
166 fsp_display_fvi_version_hob();
167
168 soc_fill_gpio_pm_configuration();
169
170 /* Swap enabled PCI ports in device tree if needed. */
171 pcie_rp_update_devicetree(get_pcie_rp_table());
Subrata Banikad42d9c2023-04-19 18:30:53 +0530172
173 /*
174 * Earlier when coreboot used to send EOP at late as possible caused
175 * issue of delayed response from CSE since CSE was busy loading payload.
176 * To resolve the issue, EOP should be sent earlier than current sequence
177 * in the boot sequence at BS_DEV_INIT.
178 *
179 * Intel CSE team recommends to send EOP close to FW init (between FSP-S
180 * exit and current boot sequence) to reduce message response time from
181 * CSE hence moving sending EOP to earlier stage.
182 */
183 if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY) ||
184 CONFIG(SOC_INTEL_CSE_SEND_EOP_ASYNC)) {
185 printk(BIOS_INFO, "Sending EOP early from SoC\n");
186 cse_send_end_of_post();
187 }
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700188}
189
Kapil Porwalcca3c902022-12-19 23:57:15 +0530190static void cpu_fill_ssdt(const struct device *dev)
191{
192 if (!generate_pin_irq_map())
193 printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n");
194
195 generate_cpu_entries(dev);
196}
197
198static void cpu_set_north_irqs(struct device *dev)
199{
200 irq_program_non_pch();
201}
202
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700203static struct device_operations pci_domain_ops = {
204 .read_resources = &pci_domain_read_resources,
205 .set_resources = &pci_domain_set_resources,
Arthur Heymans0b0113f2023-08-31 17:09:28 +0200206 .scan_bus = &pci_host_bridge_scan_bus,
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700207#if CONFIG(HAVE_ACPI_TABLES)
208 .acpi_name = &soc_acpi_name,
209 .acpi_fill_ssdt = ssdt_set_above_4g_pci,
210#endif
211};
212
213static struct device_operations cpu_bus_ops = {
214 .read_resources = noop_read_resources,
215 .set_resources = noop_set_resources,
Kapil Porwalcca3c902022-12-19 23:57:15 +0530216 .enable_resources = cpu_set_north_irqs,
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700217#if CONFIG(HAVE_ACPI_TABLES)
Kapil Porwalcca3c902022-12-19 23:57:15 +0530218 .acpi_fill_ssdt = cpu_fill_ssdt,
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700219#endif
220};
221
222static void soc_enable(struct device *dev)
223{
224 /*
225 * Set the operations if it is a special bus type or a hidden PCI
226 * device.
227 */
228 if (dev->path.type == DEVICE_PATH_DOMAIN)
229 dev->ops = &pci_domain_ops;
230 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
231 dev->ops = &cpu_bus_ops;
232 else if (dev->path.type == DEVICE_PATH_PCI &&
233 dev->path.pci.devfn == PCI_DEVFN_PMC)
234 dev->ops = &pmc_ops;
235 else if (dev->path.type == DEVICE_PATH_PCI &&
Dinesh Gehlot095043f2023-08-18 10:04:53 +0530236 dev->path.pci.devfn == PCI_DEVFN_IOE_PMC)
237 dev->ops = &ioe_pmc_ops;
238 else if (dev->path.type == DEVICE_PATH_PCI &&
Subrata Banik4ed30ca2022-10-27 15:44:54 +0530239 dev->path.pci.devfn == PCI_DEVFN_P2SB)
240 dev->ops = &soc_p2sb_ops;
241 else if (dev->path.type == DEVICE_PATH_PCI &&
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700242 dev->path.pci.devfn == PCI_DEVFN_IOE_P2SB)
243 dev->ops = &ioe_p2sb_ops;
244 else if (dev->path.type == DEVICE_PATH_GPIO)
245 block_gpio_enable(dev);
246}
247
Subrata Banik94055412023-05-17 14:33:55 +0530248static void soc_init_final_device(void *chip_info)
249{
250 uint32_t reset_status = fsp_get_pch_reset_status();
251
252 if (reset_status == FSP_SUCCESS)
253 return;
254
255 /* Handle any pending reset request from previously executed FSP APIs */
256 fsp_handle_reset(reset_status);
257
258 /* Control shouldn't return here */
lilacious40cb3fe2023-06-21 23:24:14 +0200259 die_with_post_code(POSTCODE_HW_INIT_FAILURE,
Subrata Banik94055412023-05-17 14:33:55 +0530260 "Failed to handle the FSP reset request with error 0x%08x\n", reset_status);
261}
262
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700263struct chip_operations soc_intel_meteorlake_ops = {
264 CHIP_NAME("Intel Meteorlake")
265 .enable_dev = &soc_enable,
266 .init = &soc_init_pre_device,
Subrata Banik94055412023-05-17 14:33:55 +0530267 .final = &soc_init_final_device,
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700268};