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review.coreboot.org / coreboot / c7c746c3b2cab52a80719bba39cbdc9ea4babb35 / . / src / soc / intel / meteorlake / chip.c
blob: 5b62c069daa0b0f3e792961fc47eb76ad7663251 [file] [log] [blame]
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <device/device.h>
4#include <device/pci.h>
5#include <fsp/api.h>
6#include <fsp/util.h>
7#include <intelblocks/acpi.h>
8#include <intelblocks/cfg.h>
9#include <intelblocks/gpio.h>
10#include <intelblocks/itss.h>
11#include <intelblocks/pcie_rp.h>
12#include <intelblocks/systemagent.h>
13#include <intelblocks/xdci.h>
14#include <soc/intel/common/vbt.h>
15#include <soc/itss.h>
16#include <soc/p2sb.h>
17#include <soc/pci_devs.h>
18#include <soc/pcie.h>
19#include <soc/ramstage.h>
20#include <soc/soc_chip.h>
21
22#if CONFIG(HAVE_ACPI_TABLES)
23const char *soc_acpi_name(const struct device *dev)
24{
25 if (dev->path.type == DEVICE_PATH_DOMAIN)
26 return "PCI0";
27
28 if (dev->path.type == DEVICE_PATH_USB) {
29 switch (dev->path.usb.port_type) {
30 case 0:
31 /* Root Hub */
32 return "RHUB";
33 case 2:
34 /* USB2 ports */
35 switch (dev->path.usb.port_id) {
36 case 0: return "HS01";
37 case 1: return "HS02";
38 case 2: return "HS03";
39 case 3: return "HS04";
40 case 4: return "HS05";
41 case 5: return "HS06";
42 case 6: return "HS07";
43 case 7: return "HS08";
44 case 8: return "HS09";
45 case 9: return "HS10";
46 }
47 break;
48 case 3:
49 /* USB3 ports */
50 switch (dev->path.usb.port_id) {
51 case 0: return "SS01";
52 case 1: return "SS02";
53 case 2: return "SS03";
54 case 3: return "SS04";
55 }
56 break;
57 }
58 printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.usb.port_type);
59 return NULL;
60 }
61 if (dev->path.type != DEVICE_PATH_PCI) {
62 printk(BIOS_DEBUG, "dev->path.type=%x\n", dev->path.type);
63 return NULL;
64 }
65
66 switch (dev->path.pci.devfn) {
67 case PCI_DEVFN_ROOT: return "MCHC";
68 case PCI_DEVFN_TCSS_XHCI: return "TXHC";
69 case PCI_DEVFN_TCSS_XDCI: return "TXDC";
70 case PCI_DEVFN_TCSS_DMA0: return "TDM0";
71 case PCI_DEVFN_TCSS_DMA1: return "TDM1";
72 case PCI_DEVFN_TBT0: return "TRP0";
73 case PCI_DEVFN_TBT1: return "TRP1";
74 case PCI_DEVFN_TBT2: return "TRP2";
75 case PCI_DEVFN_TBT3: return "TRP3";
76 case PCI_DEVFN_IPU: return "IPU0";
77 case PCI_DEVFN_ISH: return "ISHB";
78 case PCI_DEVFN_XHCI: return "XHCI";
79 case PCI_DEVFN_I2C0: return "I2C0";
80 case PCI_DEVFN_I2C1: return "I2C1";
81 case PCI_DEVFN_I2C2: return "I2C2";
82 case PCI_DEVFN_I2C3: return "I2C3";
83 case PCI_DEVFN_I2C4: return "I2C4";
84 case PCI_DEVFN_I2C5: return "I2C5";
85 case PCI_DEVFN_SATA: return "SATA";
86 case PCI_DEVFN_PCIE1: return "RP01";
87 case PCI_DEVFN_PCIE2: return "RP02";
88 case PCI_DEVFN_PCIE3: return "RP03";
89 case PCI_DEVFN_PCIE4: return "RP04";
90 case PCI_DEVFN_PCIE5: return "RP05";
91 case PCI_DEVFN_PCIE6: return "RP06";
92 case PCI_DEVFN_PCIE7: return "RP07";
93 case PCI_DEVFN_PCIE8: return "RP08";
94 case PCI_DEVFN_PCIE9: return "RP09";
95 case PCI_DEVFN_PCIE10: return "RP10";
96 case PCI_DEVFN_PCIE11: return "RP11";
97 case PCI_DEVFN_PCIE12: return "RP12";
98 case PCI_DEVFN_PMC: return "PMC";
99 case PCI_DEVFN_UART0: return "UAR0";
100 case PCI_DEVFN_UART1: return "UAR1";
101 case PCI_DEVFN_UART2: return "UAR2";
102 case PCI_DEVFN_GSPI0: return "SPI0";
103 case PCI_DEVFN_GSPI1: return "SPI1";
Angel Ponsc7c746c2022-07-16 12:37:38 +0200[diff] [blame^]104 case PCI_DEVFN_GSPI2: return "SPI2";
Ravi Sarawadi91ffac82022-05-07 16:37:09 -0700[diff] [blame]105 /* Keeping ACPI device name coherent with ec.asl */
106 case PCI_DEVFN_ESPI: return "LPCB";
107 case PCI_DEVFN_HDA: return "HDAS";
108 case PCI_DEVFN_SMBUS: return "SBUS";
109 case PCI_DEVFN_GBE: return "GLAN";
110 }
111 printk(BIOS_DEBUG, "dev->path.devfn=%x\n", dev->path.pci.devfn);
112 return NULL;
113}
114#endif
115
116/* SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register */
117static void soc_fill_gpio_pm_configuration(void)
118{
119 uint8_t value[TOTAL_GPIO_COMM];
120 const config_t *config = config_of_soc();
121
122 if (config->gpio_override_pm)
123 memcpy(value, config->gpio_pm, sizeof(value));
124 else
125 memset(value, MISCCFG_GPIO_PM_CONFIG_BITS, sizeof(value));
126
127 gpio_pm_configure(value, TOTAL_GPIO_COMM);
128}
129
130void soc_init_pre_device(void *chip_info)
131{
132 /* Perform silicon specific init. */
133 fsp_silicon_init();
134
135 /* Display FIRMWARE_VERSION_INFO_HOB */
136 fsp_display_fvi_version_hob();
137
138 soc_fill_gpio_pm_configuration();
139
140 /* Swap enabled PCI ports in device tree if needed. */
141 pcie_rp_update_devicetree(get_pcie_rp_table());
142}
143
144static struct device_operations pci_domain_ops = {
145 .read_resources = &pci_domain_read_resources,
146 .set_resources = &pci_domain_set_resources,
147 .scan_bus = &pci_domain_scan_bus,
148#if CONFIG(HAVE_ACPI_TABLES)
149 .acpi_name = &soc_acpi_name,
150 .acpi_fill_ssdt = ssdt_set_above_4g_pci,
151#endif
152};
153
154static struct device_operations cpu_bus_ops = {
155 .read_resources = noop_read_resources,
156 .set_resources = noop_set_resources,
157#if CONFIG(HAVE_ACPI_TABLES)
158 .acpi_fill_ssdt = generate_cpu_entries,
159#endif
160};
161
162static void soc_enable(struct device *dev)
163{
164 /*
165 * Set the operations if it is a special bus type or a hidden PCI
166 * device.
167 */
168 if (dev->path.type == DEVICE_PATH_DOMAIN)
169 dev->ops = &pci_domain_ops;
170 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
171 dev->ops = &cpu_bus_ops;
172 else if (dev->path.type == DEVICE_PATH_PCI &&
173 dev->path.pci.devfn == PCI_DEVFN_PMC)
174 dev->ops = &pmc_ops;
175 else if (dev->path.type == DEVICE_PATH_PCI &&
176 dev->path.pci.devfn == PCI_DEVFN_IOE_P2SB)
177 dev->ops = &ioe_p2sb_ops;
178 else if (dev->path.type == DEVICE_PATH_GPIO)
179 block_gpio_enable(dev);
180}
181
182struct chip_operations soc_intel_meteorlake_ops = {
183 CHIP_NAME("Intel Meteorlake")
184 .enable_dev = &soc_enable,
185 .init = &soc_init_pre_device,
186};