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Angel Ponsf94ac9a2020-04-05 15:46:48 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Duncan Lauriec88c54c2014-04-30 16:36:13 -07002
Duncan Lauriec88c54c2014-04-30 16:36:13 -07003#include <bootstate.h>
4#include <console/console.h>
5#include <console/post_codes.h>
Angel Ponsffc505b2020-10-17 17:48:56 +02006#include <device/pci_ops.h>
Julius Werner4ee4bd52014-10-20 13:46:39 -07007#include <soc/pci_devs.h>
Angel Pons071754c2020-10-23 22:35:41 +02008#include <soc/pch.h>
Julius Werner4ee4bd52014-10-20 13:46:39 -07009#include <soc/systemagent.h>
Duncan Lauriec88c54c2014-04-30 16:36:13 -070010
Angel Ponsa0cb7132020-10-17 17:40:05 +020011/*
12 * 16.6 System Agent Configuration Locking
13 * "5th Generation Intel Core Processor Family BIOS Specification"
14 * Document Number 535094
15 * Revision 2.2.0, August 2014
16 *
17 * To ease reading, first lock PCI registers, then MCHBAR registers.
18 * Write the MC Lock register first, since more than one bit gets set.
19 */
Angel Ponsffc505b2020-10-17 17:48:56 +020020static void broadwell_systemagent_finalize(void)
21{
22 struct device *const host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT);
Duncan Lauriec88c54c2014-04-30 16:36:13 -070023
Angel Pons9ab02cb2020-10-13 13:56:25 +020024 pci_or_config16(host_bridge, GGC, 1 << 0);
25 pci_or_config32(host_bridge, DPR, 1 << 0);
26 pci_or_config32(host_bridge, MESEG_LIMIT, 1 << 10);
27 pci_or_config32(host_bridge, REMAPBASE, 1 << 0);
28 pci_or_config32(host_bridge, REMAPLIMIT, 1 << 0);
29 pci_or_config32(host_bridge, TOM, 1 << 0);
30 pci_or_config32(host_bridge, TOUUD, 1 << 0);
31 pci_or_config32(host_bridge, BDSM, 1 << 0);
32 pci_or_config32(host_bridge, BGSM, 1 << 0);
33 pci_or_config32(host_bridge, TSEG, 1 << 0);
34 pci_or_config32(host_bridge, TOLUD, 1 << 0);
Angel Ponsffc505b2020-10-17 17:48:56 +020035
36 MCHBAR32(0x50fc) |= 0x8f; /* MC */
37 MCHBAR32(0x5500) |= 1 << 0; /* PAVP */
38 MCHBAR32(0x5880) |= 1 << 5; /* DDR PTM */
39 MCHBAR32(0x7000) |= 1 << 31;
40 MCHBAR32(0x77fc) |= 1 << 0;
41 MCHBAR32(0x7ffc) |= 1 << 0;
42 MCHBAR32(0x6800) |= 1 << 31;
43 MCHBAR32(0x6020) |= 1 << 0; /* UMA GFX */
44 MCHBAR32(0x63fc) |= 1 << 0; /* VTDTRK */
45
46 /* Read+write the following */
47 MCHBAR32(0x6030) = MCHBAR32(0x6030);
48 MCHBAR32(0x6034) = MCHBAR32(0x6034);
49 MCHBAR32(0x6008) = MCHBAR32(0x6008);
50}
Duncan Lauriec88c54c2014-04-30 16:36:13 -070051
Duncan Lauriec88c54c2014-04-30 16:36:13 -070052static void broadwell_finalize(void *unused)
53{
54 printk(BIOS_DEBUG, "Finalizing chipset.\n");
55
Angel Ponsffc505b2020-10-17 17:48:56 +020056 broadwell_systemagent_finalize();
Angel Ponsa0cb7132020-10-17 17:40:05 +020057
Angel Pons071754c2020-10-23 22:35:41 +020058 broadwell_pch_finalize();
Duncan Lauriec88c54c2014-04-30 16:36:13 -070059
Duncan Lauriec88c54c2014-04-30 16:36:13 -070060 /* Indicate finalize step with post code */
61 post_code(POST_OS_BOOT);
62}
63
Aaron Durbin9ef9d852015-03-16 17:30:09 -050064BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL);
65BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL);