Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 4ee4bd5bb000b5c78e3d4a3f0113fe1e46e44851 / . / src / soc / intel / broadwell / finalize.c
blob: b4c2031479e2db85a49428b7313e5fbaafd18239 [file] [log] [blame]
Duncan Lauriec88c54c2014-04-30 16:36:13 -0700[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2014 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <arch/io.h>
21#include <bootstate.h>
22#include <console/console.h>
23#include <console/post_codes.h>
24#include <cpu/x86/smm.h>
25#include <reg_script.h>
26#include <spi-generic.h>
27#include <stdlib.h>
Julius Werner4ee4bd52014-10-20 13:46:39 -0700[diff] [blame^]28#include <soc/pci_devs.h>
29#include <soc/lpc.h>
30#include <soc/me.h>
31#include <soc/rcba.h>
32#include <soc/spi.h>
33#include <soc/systemagent.h>
Duncan Lauriec88c54c2014-04-30 16:36:13 -0700[diff] [blame]34
35const struct reg_script system_agent_finalize_script[] = {
36 REG_PCI_OR16(0x50, 1 << 0), /* GGC */
37 REG_PCI_OR32(0x5c, 1 << 0), /* DPR */
38 REG_PCI_OR32(0x78, 1 << 10), /* ME */
39 REG_PCI_OR32(0x90, 1 << 0), /* REMAPBASE */
40 REG_PCI_OR32(0x98, 1 << 0), /* REMAPLIMIT */
41 REG_PCI_OR32(0xa0, 1 << 0), /* TOM */
42 REG_PCI_OR32(0xa8, 1 << 0), /* TOUUD */
43 REG_PCI_OR32(0xb0, 1 << 0), /* BDSM */
44 REG_PCI_OR32(0xb4, 1 << 0), /* BGSM */
45 REG_PCI_OR32(0xb8, 1 << 0), /* TSEGMB */
46 REG_PCI_OR32(0xbc, 1 << 0), /* TOLUD */
47 REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0), /* PAVP */
48 REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31), /* SA PM */
49 REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0), /* UMA GFX */
50 REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0), /* VTDTRK */
51 REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31),
52 REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31),
53 REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0),
54 REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f), /* MC */
55
56 REG_SCRIPT_END
57};
58
59const struct reg_script pch_finalize_script[] = {
60 /* Set SPI opcode menu */
61 REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_PREOP,
62 SPI_OPPREFIX),
63 REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_OPTYPE,
64 SPI_OPTYPE),
65 REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
66 SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER),
67 REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET +
68 SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER),
69
70 /* Lock SPIBAR */
71 REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
72 SPIBAR_HSFS_FLOCKDN),
73
74 /* TC Lockdown */
75 REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
76
77 /* BIOS Interface Lockdown */
78 REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
79
80 /* Function Disable SUS Well Lockdown */
81 REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
82
83 /* Global SMI Lock */
84 REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK),
85
86 /* GEN_PMCON Lock */
87 REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK),
88
89 /* PMSYNC */
90 REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
91
92
93 REG_SCRIPT_END
94};
95
96static void broadwell_finalize(void *unused)
97{
98 printk(BIOS_DEBUG, "Finalizing chipset.\n");
99
100 reg_script_run_on_dev(SA_DEV_ROOT, system_agent_finalize_script);
101 reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
102
Kane Chen472d0cb2014-08-21 10:36:17 -0700[diff] [blame]103 /* Lock */
104 RCBA32_OR(0x3a6c, 0x00000001);
105
Duncan Lauriec88c54c2014-04-30 16:36:13 -0700[diff] [blame]106 /* Read+Write the following registers */
107 MCHBAR32(0x6030) = MCHBAR32(0x6030);
108 MCHBAR32(0x6034) = MCHBAR32(0x6034);
109 MCHBAR32(0x6008) = MCHBAR32(0x6008);
110 RCBA32(0x21a4) = RCBA32(0x21a4);
111
112 /* Re-init SPI after lockdown */
113 spi_init();
114
115 /* Lock down management engine */
116 intel_me_finalize();
117
118 printk(BIOS_DEBUG, "Finalizing SMM.\n");
119 outb(APM_CNT_FINALIZE, APM_CNT);
120
121 /* Indicate finalize step with post code */
122 post_code(POST_OS_BOOT);
123}
124
Aaron Durbin9ef9d852015-03-16 17:30:09 -0500[diff] [blame]125BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL);
126BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL);