Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 3 | #include <bootstate.h> |
| 4 | #include <console/console.h> |
| 5 | #include <console/post_codes.h> |
Angel Pons | ffc505b | 2020-10-17 17:48:56 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 7 | #include <reg_script.h> |
| 8 | #include <spi-generic.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 9 | #include <soc/pci_devs.h> |
| 10 | #include <soc/lpc.h> |
| 11 | #include <soc/me.h> |
| 12 | #include <soc/rcba.h> |
| 13 | #include <soc/spi.h> |
| 14 | #include <soc/systemagent.h> |
Arthur Heymans | 3c1e986 | 2019-10-13 22:54:53 +0200 | [diff] [blame] | 15 | #include <southbridge/intel/common/spi.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 16 | |
Angel Pons | a0cb713 | 2020-10-17 17:40:05 +0200 | [diff] [blame] | 17 | /* |
| 18 | * 16.6 System Agent Configuration Locking |
| 19 | * "5th Generation Intel Core Processor Family BIOS Specification" |
| 20 | * Document Number 535094 |
| 21 | * Revision 2.2.0, August 2014 |
| 22 | * |
| 23 | * To ease reading, first lock PCI registers, then MCHBAR registers. |
| 24 | * Write the MC Lock register first, since more than one bit gets set. |
| 25 | */ |
Angel Pons | ffc505b | 2020-10-17 17:48:56 +0200 | [diff] [blame] | 26 | static void broadwell_systemagent_finalize(void) |
| 27 | { |
| 28 | struct device *const host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 29 | |
Angel Pons | 9ab02cb | 2020-10-13 13:56:25 +0200 | [diff] [blame^] | 30 | pci_or_config16(host_bridge, GGC, 1 << 0); |
| 31 | pci_or_config32(host_bridge, DPR, 1 << 0); |
| 32 | pci_or_config32(host_bridge, MESEG_LIMIT, 1 << 10); |
| 33 | pci_or_config32(host_bridge, REMAPBASE, 1 << 0); |
| 34 | pci_or_config32(host_bridge, REMAPLIMIT, 1 << 0); |
| 35 | pci_or_config32(host_bridge, TOM, 1 << 0); |
| 36 | pci_or_config32(host_bridge, TOUUD, 1 << 0); |
| 37 | pci_or_config32(host_bridge, BDSM, 1 << 0); |
| 38 | pci_or_config32(host_bridge, BGSM, 1 << 0); |
| 39 | pci_or_config32(host_bridge, TSEG, 1 << 0); |
| 40 | pci_or_config32(host_bridge, TOLUD, 1 << 0); |
Angel Pons | ffc505b | 2020-10-17 17:48:56 +0200 | [diff] [blame] | 41 | |
| 42 | MCHBAR32(0x50fc) |= 0x8f; /* MC */ |
| 43 | MCHBAR32(0x5500) |= 1 << 0; /* PAVP */ |
| 44 | MCHBAR32(0x5880) |= 1 << 5; /* DDR PTM */ |
| 45 | MCHBAR32(0x7000) |= 1 << 31; |
| 46 | MCHBAR32(0x77fc) |= 1 << 0; |
| 47 | MCHBAR32(0x7ffc) |= 1 << 0; |
| 48 | MCHBAR32(0x6800) |= 1 << 31; |
| 49 | MCHBAR32(0x6020) |= 1 << 0; /* UMA GFX */ |
| 50 | MCHBAR32(0x63fc) |= 1 << 0; /* VTDTRK */ |
| 51 | |
| 52 | /* Read+write the following */ |
| 53 | MCHBAR32(0x6030) = MCHBAR32(0x6030); |
| 54 | MCHBAR32(0x6034) = MCHBAR32(0x6034); |
| 55 | MCHBAR32(0x6008) = MCHBAR32(0x6008); |
| 56 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 57 | |
| 58 | const struct reg_script pch_finalize_script[] = { |
Angel Pons | 12d48cd | 2020-10-03 12:22:04 +0200 | [diff] [blame] | 59 | #if !CONFIG(EM100PRO_SPI_CONSOLE) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 60 | /* Lock SPIBAR */ |
| 61 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS, |
| 62 | SPIBAR_HSFS_FLOCKDN), |
Duncan Laurie | 9d08c4a | 2015-12-22 17:08:21 -0800 | [diff] [blame] | 63 | #endif |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 64 | |
| 65 | /* TC Lockdown */ |
| 66 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)), |
| 67 | |
| 68 | /* BIOS Interface Lockdown */ |
| 69 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)), |
| 70 | |
| 71 | /* Function Disable SUS Well Lockdown */ |
| 72 | REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)), |
| 73 | |
| 74 | /* Global SMI Lock */ |
| 75 | REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK), |
| 76 | |
| 77 | /* GEN_PMCON Lock */ |
| 78 | REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK), |
| 79 | |
| 80 | /* PMSYNC */ |
| 81 | REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)), |
| 82 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 83 | REG_SCRIPT_END |
| 84 | }; |
| 85 | |
| 86 | static void broadwell_finalize(void *unused) |
| 87 | { |
| 88 | printk(BIOS_DEBUG, "Finalizing chipset.\n"); |
| 89 | |
Angel Pons | ffc505b | 2020-10-17 17:48:56 +0200 | [diff] [blame] | 90 | broadwell_systemagent_finalize(); |
Angel Pons | a0cb713 | 2020-10-17 17:40:05 +0200 | [diff] [blame] | 91 | |
Arthur Heymans | 3c1e986 | 2019-10-13 22:54:53 +0200 | [diff] [blame] | 92 | spi_finalize_ops(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 93 | reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script); |
| 94 | |
Kane Chen | 472d0cb | 2014-08-21 10:36:17 -0700 | [diff] [blame] | 95 | /* Lock */ |
| 96 | RCBA32_OR(0x3a6c, 0x00000001); |
| 97 | |
Angel Pons | a0cb713 | 2020-10-17 17:40:05 +0200 | [diff] [blame] | 98 | /* Read+Write the following register */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 99 | RCBA32(0x21a4) = RCBA32(0x21a4); |
| 100 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 101 | /* Indicate finalize step with post code */ |
| 102 | post_code(POST_OS_BOOT); |
| 103 | } |
| 104 | |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame] | 105 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL); |
| 106 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL); |