Angel Pons | ba38f37 | 2020-04-05 15:46:45 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 3 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 4 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | #include <cbmem.h> |
| 7 | #include <console/console.h> |
| 8 | #include <device/device.h> |
| 9 | #include <device/pci.h> |
| 10 | #include <device/pci_ids.h> |
| 11 | #include <reg_script.h> |
| 12 | |
| 13 | #include <soc/iomap.h> |
| 14 | #include <soc/iosf.h> |
| 15 | #include <soc/lpc.h> |
| 16 | #include <soc/nvs.h> |
| 17 | #include <soc/pattrs.h> |
| 18 | #include <soc/pci_devs.h> |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 19 | #include <soc/pm.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 20 | #include <soc/ramstage.h> |
| 21 | #include "chip.h" |
| 22 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 23 | /* |
| 24 | * The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB |
| 25 | * address. Just take 1MiB @ 512MiB. |
| 26 | */ |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 27 | #define FIRMWARE_PHYS_BASE (512 << 20) |
Matt DeVillier | 83ef07a | 2018-01-21 16:37:24 -0600 | [diff] [blame] | 28 | #define FIRMWARE_PHYS_LENGTH (2 << 20) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 29 | #define FIRMWARE_PCI_REG_BASE 0xa8 |
| 30 | #define FIRMWARE_PCI_REG_LENGTH 0xac |
| 31 | #define FIRMWARE_REG_BASE_C0 0x144000 |
| 32 | #define FIRMWARE_REG_LENGTH_C0 (FIRMWARE_REG_BASE_C0 + 4) |
| 33 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 34 | static void assign_device_nvs(struct device *dev, u32 *field, |
| 35 | unsigned int index) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 36 | { |
| 37 | struct resource *res; |
| 38 | |
| 39 | res = find_resource(dev, index); |
| 40 | if (res) |
| 41 | *field = res->base; |
| 42 | } |
| 43 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 44 | static void lpe_enable_acpi_mode(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 45 | { |
| 46 | static const struct reg_script ops[] = { |
| 47 | /* Disable PCI interrupt, enable Memory and Bus Master */ |
| 48 | REG_PCI_OR32(PCI_COMMAND, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 49 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE), |
| 50 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 51 | /* Enable ACPI mode */ |
| 52 | REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1, |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 53 | LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN), |
| 54 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 55 | REG_SCRIPT_END |
| 56 | }; |
| 57 | global_nvs_t *gnvs; |
| 58 | |
| 59 | /* Find ACPI NVS to update BARs */ |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 60 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 61 | if (!gnvs) { |
| 62 | printk(BIOS_ERR, "Unable to locate Global NVS\n"); |
| 63 | return; |
| 64 | } |
| 65 | |
| 66 | /* Save BAR0, BAR1, and firmware base to ACPI NVS */ |
| 67 | assign_device_nvs(dev, &gnvs->dev.lpe_bar0, PCI_BASE_ADDRESS_0); |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 68 | assign_device_nvs(dev, &gnvs->dev.lpe_bar1, PCI_BASE_ADDRESS_2); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 69 | assign_device_nvs(dev, &gnvs->dev.lpe_fw, FIRMWARE_PCI_REG_BASE); |
| 70 | |
| 71 | /* Device is enabled in ACPI mode */ |
| 72 | gnvs->dev.lpe_en = 1; |
| 73 | |
| 74 | /* Put device in ACPI mode */ |
| 75 | reg_script_run_on_dev(dev, ops); |
| 76 | } |
| 77 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 78 | static void setup_codec_clock(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 79 | { |
| 80 | uint32_t reg; |
| 81 | u32 *clk_reg; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 82 | struct soc_intel_braswell_config *config; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 83 | const char *freq_str; |
| 84 | |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 85 | config = config_of(dev); |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 86 | switch (config->lpe_codec_clk_src) { |
| 87 | case LPE_CLK_SRC_XTAL: |
| 88 | /* XTAL driven bit2=0 */ |
| 89 | freq_str = "19.2MHz External Crystal"; |
| 90 | reg = CLK_SRC_XTAL; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 91 | break; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 92 | |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 93 | case LPE_CLK_SRC_PLL: |
| 94 | /* PLL driven bit2=1 */ |
| 95 | freq_str = "19.2MHz PLL"; |
| 96 | reg = CLK_SRC_PLL; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 97 | break; |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 98 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 99 | default: |
fdurairx | aff502e | 2015-08-21 15:36:53 -0700 | [diff] [blame] | 100 | reg = CLK_SRC_XTAL; |
| 101 | printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n"); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 102 | return; |
| 103 | } |
| 104 | |
| 105 | /* Default to always running. */ |
| 106 | reg |= CLK_CTL_ON; |
| 107 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 108 | |
| 109 | printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); |
| 110 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 111 | clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 112 | |
| 113 | write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); |
| 114 | } |
| 115 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 116 | static void lpe_stash_firmware_info(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 117 | { |
| 118 | struct resource *res; |
| 119 | struct resource *mmio; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 120 | |
| 121 | res = find_resource(dev, FIRMWARE_PCI_REG_BASE); |
| 122 | if (res == NULL) { |
| 123 | printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); |
| 124 | return; |
| 125 | } |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 126 | printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 127 | |
| 128 | /* Continue using old way of informing firmware address / size. */ |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 129 | pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 130 | pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size); |
| 131 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 132 | /* Also put the address in MMIO space like on C0 BTM */ |
| 133 | mmio = find_resource(dev, PCI_BASE_ADDRESS_0); |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 134 | write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); |
| 135 | write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 136 | } |
| 137 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 138 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 139 | static void lpe_init(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 140 | { |
Kyösti Mälkki | 8950cfb | 2019-07-13 22:16:25 +0300 | [diff] [blame] | 141 | struct soc_intel_braswell_config *config = config_of(dev); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 142 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 143 | printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 144 | |
| 145 | lpe_stash_firmware_info(dev); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 146 | setup_codec_clock(dev); |
| 147 | |
| 148 | if (config->lpe_acpi_mode) |
| 149 | lpe_enable_acpi_mode(dev); |
| 150 | } |
| 151 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 152 | static void lpe_read_resources(struct device *dev) |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 153 | { |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 154 | struct resource *res; |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 155 | pci_dev_read_resources(dev); |
| 156 | |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 157 | /* |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 158 | * Allocate the BAR1 resource at index 2 to fulfill the Windows driver |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 159 | * interface requirements even though the PCI device has only one BAR |
| 160 | */ |
| 161 | res = new_resource(dev, PCI_BASE_ADDRESS_2); |
| 162 | res->base = 0; |
| 163 | res->size = 0x1000; |
| 164 | res->limit = 0xffffffff; |
| 165 | res->gran = 12; |
| 166 | res->align = 12; |
| 167 | res->flags = IORESOURCE_MEM; |
| 168 | |
Angel Pons | aee7ab2 | 2020-03-19 00:31:58 +0100 | [diff] [blame] | 169 | reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 170 | FIRMWARE_PHYS_LENGTH >> 10); |
| 171 | } |
| 172 | |
Elyes HAOUAS | b13fac3 | 2018-05-24 22:29:44 +0200 | [diff] [blame] | 173 | static void lpe_set_resources(struct device *dev) |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 174 | { |
| 175 | struct resource *res; |
| 176 | |
| 177 | res = find_resource(dev, PCI_BASE_ADDRESS_2); |
| 178 | if (res != NULL) |
| 179 | res->flags |= IORESOURCE_STORED; |
| 180 | |
| 181 | pci_dev_set_resources(dev); |
| 182 | } |
| 183 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 184 | static const struct device_operations device_ops = { |
| 185 | .read_resources = lpe_read_resources, |
Matt DeVillier | 5d6ab45 | 2018-01-17 19:39:52 -0600 | [diff] [blame] | 186 | .set_resources = lpe_set_resources, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 187 | .enable_resources = pci_dev_enable_resources, |
| 188 | .init = lpe_init, |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 189 | .ops_pci = &soc_pci_ops, |
| 190 | }; |
| 191 | |
| 192 | static const struct pci_driver southcluster __pci_driver = { |
| 193 | .ops = &device_ops, |
| 194 | .vendor = PCI_VENDOR_ID_INTEL, |
| 195 | .device = LPE_DEVID, |
| 196 | }; |