Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 3 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 4 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 5 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | Name(_BBN, 0) |
| 7 | |
| 8 | Device (MCHC) |
| 9 | { |
| 10 | Name(_ADR, 0x00000000) // 0:0.0 |
| 11 | |
| 12 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 13 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 14 | { |
| 15 | Offset (0x40), // EPBAR |
| 16 | EPEN, 1, // Enable |
| 17 | , 11, // |
Angel Pons | 05f996d | 2020-07-06 22:10:37 +0200 | [diff] [blame^] | 18 | EPBR, 27, // EPBAR |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | |
| 20 | Offset (0x48), // MCHBAR |
| 21 | MHEN, 1, // Enable |
Angel Pons | 05f996d | 2020-07-06 22:10:37 +0200 | [diff] [blame^] | 22 | , 14, // |
| 23 | MHBR, 24, // MCHBAR |
Chris Morgan | 5e5e789 | 2020-02-07 09:40:42 -0600 | [diff] [blame] | 24 | Offset (0x54), |
| 25 | DVEN, 32, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 26 | Offset (0x60), // PCIe BAR |
| 27 | PXEN, 1, // Enable |
| 28 | PXSZ, 2, // BAR size |
| 29 | , 23, // |
Angel Pons | 05f996d | 2020-07-06 22:10:37 +0200 | [diff] [blame^] | 30 | PXBR, 13, // PCIe BAR |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 31 | |
| 32 | Offset (0x68), // DMIBAR |
| 33 | DMEN, 1, // Enable |
| 34 | , 11, // |
Angel Pons | 05f996d | 2020-07-06 22:10:37 +0200 | [diff] [blame^] | 35 | DMBR, 27, // DMIBAR |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | |
| 37 | Offset (0x70), // ME Base Address |
| 38 | MEBA, 64, |
| 39 | |
| 40 | // ... |
| 41 | |
| 42 | Offset (0x80), // PAM0 |
| 43 | , 4, |
| 44 | PM0H, 2, |
| 45 | , 2, |
| 46 | Offset (0x81), // PAM1 |
| 47 | PM1L, 2, |
| 48 | , 2, |
| 49 | PM1H, 2, |
| 50 | , 2, |
| 51 | Offset (0x82), // PAM2 |
| 52 | PM2L, 2, |
| 53 | , 2, |
| 54 | PM2H, 2, |
| 55 | , 2, |
| 56 | Offset (0x83), // PAM3 |
| 57 | PM3L, 2, |
| 58 | , 2, |
| 59 | PM3H, 2, |
| 60 | , 2, |
| 61 | Offset (0x84), // PAM4 |
| 62 | PM4L, 2, |
| 63 | , 2, |
| 64 | PM4H, 2, |
| 65 | , 2, |
| 66 | Offset (0x85), // PAM5 |
| 67 | PM5L, 2, |
| 68 | , 2, |
| 69 | PM5H, 2, |
| 70 | , 2, |
| 71 | Offset (0x86), // PAM6 |
| 72 | PM6L, 2, |
| 73 | , 2, |
| 74 | PM6H, 2, |
| 75 | , 2, |
| 76 | |
| 77 | Offset (0xa0), // Top of Used Memory |
| 78 | TOM, 64, |
| 79 | |
| 80 | Offset (0xbc), // Top of Low Used Memory |
| 81 | TLUD, 32, |
| 82 | } |
| 83 | |
| 84 | Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ |
| 85 | Name (CTCC, 0) /* CTDP Current Selection */ |
| 86 | Name (CTCN, 0) /* CTDP Nominal Select */ |
| 87 | Name (CTCD, 1) /* CTDP Down Select */ |
| 88 | Name (CTCU, 2) /* CTDP Up Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 89 | Name (SPL1, 0) /* Saved PL1 value */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 90 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 91 | OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 92 | Field (MCHB, DWordAcc, Lock, Preserve) |
| 93 | { |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 94 | Offset (0x930), /* PACKAGE_POWER_SKU */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 95 | CTDN, 15, /* CTDP Nominal PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 96 | Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ |
| 97 | PUNI, 4, /* Power Units */ |
| 98 | , 4, |
| 99 | EUNI, 5, /* Energy Units */ |
| 100 | , 3, |
| 101 | TUNI, 4, /* Time Units */ |
| 102 | Offset (0x958), /* PLATFORM_INFO */ |
| 103 | , 40, |
| 104 | LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ |
| 105 | Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 106 | PL1V, 15, /* Power Limit 1 Value */ |
| 107 | PL1E, 1, /* Power Limit 1 Enable */ |
| 108 | PL1C, 1, /* Power Limit 1 Clamp */ |
| 109 | PL1T, 7, /* Power Limit 1 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 110 | Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 111 | PL2V, 15, /* Power Limit 2 Value */ |
| 112 | PL2E, 1, /* Power Limit 2 Enable */ |
| 113 | PL2C, 1, /* Power Limit 2 Clamp */ |
| 114 | PL2T, 7, /* Power Limit 2 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 115 | Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 116 | TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 117 | Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 118 | CTDD, 15, /* CTDP Down PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 119 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 120 | TARD, 8, /* CTDP Down Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 121 | Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 122 | CTDU, 15, /* CTDP Up PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 123 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 124 | TARU, 8, /* CTDP Up Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 125 | Offset (0xf50), /* CONFIG_TDP_CONTROL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | CTCS, 2, /* CTDP Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 127 | Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 128 | TARS, 8, /* Turbo Activation Ratio Select */ |
| 129 | } |
| 130 | |
| 131 | /* |
Elyes HAOUAS | 69d658f | 2016-09-17 20:32:07 +0200 | [diff] [blame] | 132 | * Search CPU0 _PSS looking for control = arg0 and then |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 133 | * return previous P-state entry number for new _PPC |
| 134 | * |
| 135 | * Format of _PSS: |
| 136 | * Name (_PSS, Package () { |
| 137 | * Package (6) { freq, power, tlat, blat, control, status } |
| 138 | * } |
| 139 | */ |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 140 | External (\_SB.CP00._PSS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | Method (PSSS, 1, NotSerialized) |
| 142 | { |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 143 | Local0 = One /* Start at P1 */ |
| 144 | Local1 = SizeOf (\_SB.CP00._PSS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 145 | |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 146 | While (Local0 < Local1) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 147 | /* Store _PSS entry Control value to Local2 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 148 | Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 |
| 149 | If (Local2 == Arg0) { |
| 150 | Return (Local0 - 1) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 151 | } |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 152 | Local0++ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | Return (0) |
| 156 | } |
| 157 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 158 | /* Calculate PL2 based on chip type */ |
| 159 | Method (CPL2, 1, NotSerialized) |
| 160 | { |
| 161 | If (\ISLP ()) { |
| 162 | /* Haswell ULT PL2 = 25W */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 163 | Return (25 * 8) |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 164 | } Else { |
| 165 | /* Haswell Mobile PL2 = 1.25 * PL1 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 166 | Return ((Arg0 * 125) / 100) |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 167 | } |
| 168 | } |
| 169 | |
| 170 | /* Set Config TDP Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 171 | Method (STND, 0, Serialized) |
| 172 | { |
| 173 | If (Acquire (CTCM, 100)) { |
| 174 | Return (0) |
| 175 | } |
| 176 | If (LEqual (CTCD, CTCC)) { |
| 177 | Release (CTCM) |
| 178 | Return (0) |
| 179 | } |
| 180 | |
| 181 | Store ("Set TDP Down", Debug) |
| 182 | |
| 183 | /* Set CTC */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 184 | CTCS = CTCD |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 185 | |
| 186 | /* Set TAR */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 187 | TARS = TARD |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 188 | |
| 189 | /* Set PPC limit and notify OS */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 190 | PPCM = PSSS (TARD) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 191 | PPCN () |
| 192 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 193 | /* Set PL2 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 194 | PL2V = CPL2 (CTDD) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 195 | |
| 196 | /* Set PL1 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 197 | PL1V = CTDD |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 198 | |
| 199 | /* Store the new TDP Down setting */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 200 | CTCC = CTCD |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 201 | |
| 202 | Release (CTCM) |
| 203 | Return (1) |
| 204 | } |
| 205 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 206 | /* Set Config TDP Nominal from Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 207 | Method (STDN, 0, Serialized) |
| 208 | { |
| 209 | If (Acquire (CTCM, 100)) { |
| 210 | Return (0) |
| 211 | } |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 212 | If (CTCN == CTCC) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 213 | Release (CTCM) |
| 214 | Return (0) |
| 215 | } |
| 216 | |
| 217 | Store ("Set TDP Nominal", Debug) |
| 218 | |
| 219 | /* Set PL1 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 220 | PL1V = CTDN |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 221 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 222 | /* Set PL2 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 223 | PL2V = CPL2 (CTDN) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 224 | |
| 225 | /* Set PPC limit and notify OS */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 226 | PPCM = PSSS (TARN) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 227 | PPCN () |
| 228 | |
| 229 | /* Set TAR */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 230 | TARS = TARN |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 231 | |
| 232 | /* Set CTC */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 233 | CTCS = CTCN |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 234 | |
| 235 | /* Store the new TDP Nominal setting */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 236 | CTCC = CTCN |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 237 | |
| 238 | Release (CTCM) |
| 239 | Return (1) |
| 240 | } |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 241 | |
| 242 | /* Calculate PL1 value based on requested TDP */ |
| 243 | Method (TDPP, 1, NotSerialized) |
| 244 | { |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 245 | Return (((PUNI - 1) << 2) * Arg0) |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 246 | } |
| 247 | |
| 248 | /* Enable Controllable TDP to limit PL1 to requested value */ |
| 249 | Method (CTLE, 1, Serialized) |
| 250 | { |
| 251 | If (Acquire (CTCM, 100)) { |
| 252 | Return (0) |
| 253 | } |
| 254 | |
| 255 | Store ("Enable PL1 Limit", Debug) |
| 256 | |
| 257 | /* Set _PPC to LFM */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 258 | Local0 = PSSS (LFM_) |
| 259 | PPCM = Local0 + 1 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 260 | \PPCN () |
| 261 | |
| 262 | /* Set TAR to LFM-1 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 263 | TARS = LFM_ - 1 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 264 | |
| 265 | /* Set PL1 to desired value */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 266 | SPL1 = PL1V |
| 267 | PL1V = TDPP (Arg0) |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 268 | |
| 269 | /* Set PL1 CLAMP bit */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 270 | PL1C = 1 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 271 | |
| 272 | Release (CTCM) |
| 273 | Return (1) |
| 274 | } |
| 275 | |
| 276 | /* Disable Controllable TDP */ |
| 277 | Method (CTLD, 0, Serialized) |
| 278 | { |
| 279 | If (Acquire (CTCM, 100)) { |
| 280 | Return (0) |
| 281 | } |
| 282 | |
| 283 | Store ("Disable PL1 Limit", Debug) |
| 284 | |
| 285 | /* Clear PL1 CLAMP bit */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 286 | PL1C = 0 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 287 | |
| 288 | /* Set PL1 to normal value */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 289 | PL1V = SPL1 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 290 | |
| 291 | /* Set TAR to 0 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 292 | TARS = 0 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 293 | |
| 294 | /* Set _PPC to 0 */ |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 295 | PPCM = 0 |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 296 | \PPCN () |
| 297 | |
| 298 | Release (CTCM) |
| 299 | Return (1) |
| 300 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 301 | } |
| 302 | |
| 303 | // Current Resource Settings |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 304 | Name (MCRS, ResourceTemplate() |
| 305 | { |
| 306 | // Bus Numbers |
| 307 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 308 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 309 | |
| 310 | // IO Region 0 |
| 311 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 312 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 313 | |
| 314 | // PCI Config Space |
| 315 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 316 | |
| 317 | // IO Region 1 |
| 318 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 319 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 320 | |
| 321 | // VGA memory (0xa0000-0xbffff) |
| 322 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 323 | Cacheable, ReadWrite, |
| 324 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 325 | 0x00020000,,, ASEG) |
| 326 | |
| 327 | // OPROM reserved (0xc0000-0xc3fff) |
| 328 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 329 | Cacheable, ReadWrite, |
| 330 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 331 | 0x00004000,,, OPR0) |
| 332 | |
| 333 | // OPROM reserved (0xc4000-0xc7fff) |
| 334 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 335 | Cacheable, ReadWrite, |
| 336 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 337 | 0x00004000,,, OPR1) |
| 338 | |
| 339 | // OPROM reserved (0xc8000-0xcbfff) |
| 340 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 341 | Cacheable, ReadWrite, |
| 342 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 343 | 0x00004000,,, OPR2) |
| 344 | |
| 345 | // OPROM reserved (0xcc000-0xcffff) |
| 346 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 347 | Cacheable, ReadWrite, |
| 348 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 349 | 0x00004000,,, OPR3) |
| 350 | |
| 351 | // OPROM reserved (0xd0000-0xd3fff) |
| 352 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 353 | Cacheable, ReadWrite, |
| 354 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 355 | 0x00004000,,, OPR4) |
| 356 | |
| 357 | // OPROM reserved (0xd4000-0xd7fff) |
| 358 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 359 | Cacheable, ReadWrite, |
| 360 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 361 | 0x00004000,,, OPR5) |
| 362 | |
| 363 | // OPROM reserved (0xd8000-0xdbfff) |
| 364 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 365 | Cacheable, ReadWrite, |
| 366 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 367 | 0x00004000,,, OPR6) |
| 368 | |
| 369 | // OPROM reserved (0xdc000-0xdffff) |
| 370 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 371 | Cacheable, ReadWrite, |
| 372 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 373 | 0x00004000,,, OPR7) |
| 374 | |
| 375 | // BIOS Extension (0xe0000-0xe3fff) |
| 376 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 377 | Cacheable, ReadWrite, |
| 378 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 379 | 0x00004000,,, ESG0) |
| 380 | |
| 381 | // BIOS Extension (0xe4000-0xe7fff) |
| 382 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 383 | Cacheable, ReadWrite, |
| 384 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 385 | 0x00004000,,, ESG1) |
| 386 | |
| 387 | // BIOS Extension (0xe8000-0xebfff) |
| 388 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 389 | Cacheable, ReadWrite, |
| 390 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 391 | 0x00004000,,, ESG2) |
| 392 | |
| 393 | // BIOS Extension (0xec000-0xeffff) |
| 394 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 395 | Cacheable, ReadWrite, |
| 396 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 397 | 0x00004000,,, ESG3) |
| 398 | |
| 399 | // System BIOS (0xf0000-0xfffff) |
| 400 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 401 | Cacheable, ReadWrite, |
| 402 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 403 | 0x00010000,,, FSEG) |
| 404 | |
| 405 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
| 406 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 407 | Cacheable, ReadWrite, |
| 408 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 409 | 0x00000000,,, PM01) |
| 410 | |
| 411 | // TPM Area (0xfed40000-0xfed44fff) |
| 412 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 413 | Cacheable, ReadWrite, |
| 414 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 415 | 0x00005000,,, TPMR) |
| 416 | }) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 417 | |
| 418 | Method (_CRS, 0, Serialized) |
| 419 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 420 | // Find PCI resource area in MCRS |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 421 | CreateDwordField(MCRS, ^PM01._MIN, PMIN) |
| 422 | CreateDwordField(MCRS, ^PM01._MAX, PMAX) |
| 423 | CreateDwordField(MCRS, ^PM01._LEN, PLEN) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 424 | |
| 425 | // Fix up PCI memory region |
| 426 | // Start with Top of Lower Usable DRAM |
Furquan Shaikh | 506479d | 2020-06-01 13:27:16 -0700 | [diff] [blame] | 427 | // Lower 20 bits of TOLUD register need to be masked since they contain lock and |
| 428 | // reserved bits. |
| 429 | Local0 = ^MCHC.TLUD & (0xfff << 20) |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 430 | Local1 = ^MCHC.MEBA |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 431 | |
| 432 | // Check if ME base is equal |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 433 | If (Local0 == Local1) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 434 | // Use Top Of Memory instead |
Furquan Shaikh | 506479d | 2020-06-01 13:27:16 -0700 | [diff] [blame] | 435 | // Lower 20 bits of TOM register need to be masked since they contain lock and |
| 436 | // reserved bits. |
| 437 | Local0 = ^MCHC.TOM & (0x7ffff << 20) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 438 | } |
| 439 | |
Furquan Shaikh | 181e2d4 | 2020-06-01 13:03:45 -0700 | [diff] [blame] | 440 | PMIN = Local0 |
| 441 | PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 |
| 442 | PLEN = PMAX - PMIN + 1 |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 443 | |
| 444 | Return (MCRS) |
| 445 | } |