Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | |
| 18 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 19 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 20 | |
| 21 | Name(_ADR, 0) |
| 22 | Name(_BBN, 0) |
| 23 | |
| 24 | Device (MCHC) |
| 25 | { |
| 26 | Name(_ADR, 0x00000000) // 0:0.0 |
| 27 | |
| 28 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 29 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 30 | { |
| 31 | Offset (0x40), // EPBAR |
| 32 | EPEN, 1, // Enable |
| 33 | , 11, // |
| 34 | EPBR, 24, // EPBAR |
| 35 | |
| 36 | Offset (0x48), // MCHBAR |
| 37 | MHEN, 1, // Enable |
| 38 | , 13, // |
| 39 | MHBR, 22, // MCHBAR |
| 40 | |
| 41 | Offset (0x60), // PCIe BAR |
| 42 | PXEN, 1, // Enable |
| 43 | PXSZ, 2, // BAR size |
| 44 | , 23, // |
| 45 | PXBR, 10, // PCIe BAR |
| 46 | |
| 47 | Offset (0x68), // DMIBAR |
| 48 | DMEN, 1, // Enable |
| 49 | , 11, // |
| 50 | DMBR, 24, // DMIBAR |
| 51 | |
| 52 | Offset (0x70), // ME Base Address |
| 53 | MEBA, 64, |
| 54 | |
| 55 | // ... |
| 56 | |
| 57 | Offset (0x80), // PAM0 |
| 58 | , 4, |
| 59 | PM0H, 2, |
| 60 | , 2, |
| 61 | Offset (0x81), // PAM1 |
| 62 | PM1L, 2, |
| 63 | , 2, |
| 64 | PM1H, 2, |
| 65 | , 2, |
| 66 | Offset (0x82), // PAM2 |
| 67 | PM2L, 2, |
| 68 | , 2, |
| 69 | PM2H, 2, |
| 70 | , 2, |
| 71 | Offset (0x83), // PAM3 |
| 72 | PM3L, 2, |
| 73 | , 2, |
| 74 | PM3H, 2, |
| 75 | , 2, |
| 76 | Offset (0x84), // PAM4 |
| 77 | PM4L, 2, |
| 78 | , 2, |
| 79 | PM4H, 2, |
| 80 | , 2, |
| 81 | Offset (0x85), // PAM5 |
| 82 | PM5L, 2, |
| 83 | , 2, |
| 84 | PM5H, 2, |
| 85 | , 2, |
| 86 | Offset (0x86), // PAM6 |
| 87 | PM6L, 2, |
| 88 | , 2, |
| 89 | PM6H, 2, |
| 90 | , 2, |
| 91 | |
| 92 | Offset (0xa0), // Top of Used Memory |
| 93 | TOM, 64, |
| 94 | |
| 95 | Offset (0xbc), // Top of Low Used Memory |
| 96 | TLUD, 32, |
| 97 | } |
| 98 | |
| 99 | Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ |
| 100 | Name (CTCC, 0) /* CTDP Current Selection */ |
| 101 | Name (CTCN, 0) /* CTDP Nominal Select */ |
| 102 | Name (CTCD, 1) /* CTDP Down Select */ |
| 103 | Name (CTCU, 2) /* CTDP Up Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 104 | Name (SPL1, 0) /* Saved PL1 value */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 105 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 106 | OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | Field (MCHB, DWordAcc, Lock, Preserve) |
| 108 | { |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 109 | Offset (0x930), /* PACKAGE_POWER_SKU */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 110 | CTDN, 15, /* CTDP Nominal PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 111 | Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ |
| 112 | PUNI, 4, /* Power Units */ |
| 113 | , 4, |
| 114 | EUNI, 5, /* Energy Units */ |
| 115 | , 3, |
| 116 | TUNI, 4, /* Time Units */ |
| 117 | Offset (0x958), /* PLATFORM_INFO */ |
| 118 | , 40, |
| 119 | LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ |
| 120 | Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 121 | PL1V, 15, /* Power Limit 1 Value */ |
| 122 | PL1E, 1, /* Power Limit 1 Enable */ |
| 123 | PL1C, 1, /* Power Limit 1 Clamp */ |
| 124 | PL1T, 7, /* Power Limit 1 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 125 | Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | PL2V, 15, /* Power Limit 2 Value */ |
| 127 | PL2E, 1, /* Power Limit 2 Enable */ |
| 128 | PL2C, 1, /* Power Limit 2 Clamp */ |
| 129 | PL2T, 7, /* Power Limit 2 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 130 | Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 131 | TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 132 | Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 133 | CTDD, 15, /* CTDP Down PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 134 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | TARD, 8, /* CTDP Down Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 136 | Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 137 | CTDU, 15, /* CTDP Up PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 138 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 139 | TARU, 8, /* CTDP Up Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 140 | Offset (0xf50), /* CONFIG_TDP_CONTROL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | CTCS, 2, /* CTDP Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 142 | Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 143 | TARS, 8, /* Turbo Activation Ratio Select */ |
| 144 | } |
| 145 | |
| 146 | /* |
Elyes HAOUAS | 69d658f | 2016-09-17 20:32:07 +0200 | [diff] [blame^] | 147 | * Search CPU0 _PSS looking for control = arg0 and then |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | * return previous P-state entry number for new _PPC |
| 149 | * |
| 150 | * Format of _PSS: |
| 151 | * Name (_PSS, Package () { |
| 152 | * Package (6) { freq, power, tlat, blat, control, status } |
| 153 | * } |
| 154 | */ |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 155 | External (\_PR.CP00._PSS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 156 | Method (PSSS, 1, NotSerialized) |
| 157 | { |
| 158 | Store (One, Local0) /* Start at P1 */ |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 159 | Store (SizeOf (\_PR.CP00._PSS), Local1) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 160 | |
| 161 | While (LLess (Local0, Local1)) { |
| 162 | /* Store _PSS entry Control value to Local2 */ |
| 163 | ShiftRight (DeRefOf (Index (DeRefOf (Index |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 164 | (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 165 | If (LEqual (Local2, Arg0)) { |
| 166 | Return (Subtract (Local0, 1)) |
| 167 | } |
| 168 | Increment (Local0) |
| 169 | } |
| 170 | |
| 171 | Return (0) |
| 172 | } |
| 173 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 174 | /* Calculate PL2 based on chip type */ |
| 175 | Method (CPL2, 1, NotSerialized) |
| 176 | { |
| 177 | If (\ISLP ()) { |
| 178 | /* Haswell ULT PL2 = 25W */ |
| 179 | Return (Multiply (25, 8)) |
| 180 | } Else { |
| 181 | /* Haswell Mobile PL2 = 1.25 * PL1 */ |
| 182 | Return (Divide (Multiply (Arg0, 125), 100)) |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | /* Set Config TDP Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 187 | Method (STND, 0, Serialized) |
| 188 | { |
| 189 | If (Acquire (CTCM, 100)) { |
| 190 | Return (0) |
| 191 | } |
| 192 | If (LEqual (CTCD, CTCC)) { |
| 193 | Release (CTCM) |
| 194 | Return (0) |
| 195 | } |
| 196 | |
| 197 | Store ("Set TDP Down", Debug) |
| 198 | |
| 199 | /* Set CTC */ |
| 200 | Store (CTCD, CTCS) |
| 201 | |
| 202 | /* Set TAR */ |
| 203 | Store (TARD, TARS) |
| 204 | |
| 205 | /* Set PPC limit and notify OS */ |
| 206 | Store (PSSS (TARD), PPCM) |
| 207 | PPCN () |
| 208 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 209 | /* Set PL2 */ |
| 210 | Store (CPL2 (CTDD), PL2V) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 211 | |
| 212 | /* Set PL1 */ |
| 213 | Store (CTDD, PL1V) |
| 214 | |
| 215 | /* Store the new TDP Down setting */ |
| 216 | Store (CTCD, CTCC) |
| 217 | |
| 218 | Release (CTCM) |
| 219 | Return (1) |
| 220 | } |
| 221 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 222 | /* Set Config TDP Nominal from Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 223 | Method (STDN, 0, Serialized) |
| 224 | { |
| 225 | If (Acquire (CTCM, 100)) { |
| 226 | Return (0) |
| 227 | } |
| 228 | If (LEqual (CTCN, CTCC)) { |
| 229 | Release (CTCM) |
| 230 | Return (0) |
| 231 | } |
| 232 | |
| 233 | Store ("Set TDP Nominal", Debug) |
| 234 | |
| 235 | /* Set PL1 */ |
| 236 | Store (CTDN, PL1V) |
| 237 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 238 | /* Set PL2 */ |
| 239 | Store (CPL2 (CTDN), PL2V) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 240 | |
| 241 | /* Set PPC limit and notify OS */ |
| 242 | Store (PSSS (TARN), PPCM) |
| 243 | PPCN () |
| 244 | |
| 245 | /* Set TAR */ |
| 246 | Store (TARN, TARS) |
| 247 | |
| 248 | /* Set CTC */ |
| 249 | Store (CTCN, CTCS) |
| 250 | |
| 251 | /* Store the new TDP Nominal setting */ |
| 252 | Store (CTCN, CTCC) |
| 253 | |
| 254 | Release (CTCM) |
| 255 | Return (1) |
| 256 | } |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 257 | |
| 258 | /* Calculate PL1 value based on requested TDP */ |
| 259 | Method (TDPP, 1, NotSerialized) |
| 260 | { |
| 261 | Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0)) |
| 262 | } |
| 263 | |
| 264 | /* Enable Controllable TDP to limit PL1 to requested value */ |
| 265 | Method (CTLE, 1, Serialized) |
| 266 | { |
| 267 | If (Acquire (CTCM, 100)) { |
| 268 | Return (0) |
| 269 | } |
| 270 | |
| 271 | Store ("Enable PL1 Limit", Debug) |
| 272 | |
| 273 | /* Set _PPC to LFM */ |
| 274 | Store (PSSS (LFM_), Local0) |
| 275 | Add (Local0, 1, PPCM) |
| 276 | \PPCN () |
| 277 | |
| 278 | /* Set TAR to LFM-1 */ |
| 279 | Subtract (LFM_, 1, TARS) |
| 280 | |
| 281 | /* Set PL1 to desired value */ |
| 282 | Store (PL1V, SPL1) |
| 283 | Store (TDPP (Arg0), PL1V) |
| 284 | |
| 285 | /* Set PL1 CLAMP bit */ |
| 286 | Store (One, PL1C) |
| 287 | |
| 288 | Release (CTCM) |
| 289 | Return (1) |
| 290 | } |
| 291 | |
| 292 | /* Disable Controllable TDP */ |
| 293 | Method (CTLD, 0, Serialized) |
| 294 | { |
| 295 | If (Acquire (CTCM, 100)) { |
| 296 | Return (0) |
| 297 | } |
| 298 | |
| 299 | Store ("Disable PL1 Limit", Debug) |
| 300 | |
| 301 | /* Clear PL1 CLAMP bit */ |
| 302 | Store (Zero, PL1C) |
| 303 | |
| 304 | /* Set PL1 to normal value */ |
| 305 | Store (SPL1, PL1V) |
| 306 | |
| 307 | /* Set TAR to 0 */ |
| 308 | Store (Zero, TARS) |
| 309 | |
| 310 | /* Set _PPC to 0 */ |
| 311 | Store (Zero, PPCM) |
| 312 | \PPCN () |
| 313 | |
| 314 | Release (CTCM) |
| 315 | Return (1) |
| 316 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 317 | } |
| 318 | |
| 319 | // Current Resource Settings |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 320 | Name (MCRS, ResourceTemplate() |
| 321 | { |
| 322 | // Bus Numbers |
| 323 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 324 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 325 | |
| 326 | // IO Region 0 |
| 327 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 328 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 329 | |
| 330 | // PCI Config Space |
| 331 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 332 | |
| 333 | // IO Region 1 |
| 334 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 335 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 336 | |
| 337 | // VGA memory (0xa0000-0xbffff) |
| 338 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 339 | Cacheable, ReadWrite, |
| 340 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 341 | 0x00020000,,, ASEG) |
| 342 | |
| 343 | // OPROM reserved (0xc0000-0xc3fff) |
| 344 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 345 | Cacheable, ReadWrite, |
| 346 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 347 | 0x00004000,,, OPR0) |
| 348 | |
| 349 | // OPROM reserved (0xc4000-0xc7fff) |
| 350 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 351 | Cacheable, ReadWrite, |
| 352 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 353 | 0x00004000,,, OPR1) |
| 354 | |
| 355 | // OPROM reserved (0xc8000-0xcbfff) |
| 356 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 357 | Cacheable, ReadWrite, |
| 358 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 359 | 0x00004000,,, OPR2) |
| 360 | |
| 361 | // OPROM reserved (0xcc000-0xcffff) |
| 362 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 363 | Cacheable, ReadWrite, |
| 364 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 365 | 0x00004000,,, OPR3) |
| 366 | |
| 367 | // OPROM reserved (0xd0000-0xd3fff) |
| 368 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 369 | Cacheable, ReadWrite, |
| 370 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 371 | 0x00004000,,, OPR4) |
| 372 | |
| 373 | // OPROM reserved (0xd4000-0xd7fff) |
| 374 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 375 | Cacheable, ReadWrite, |
| 376 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 377 | 0x00004000,,, OPR5) |
| 378 | |
| 379 | // OPROM reserved (0xd8000-0xdbfff) |
| 380 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 381 | Cacheable, ReadWrite, |
| 382 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 383 | 0x00004000,,, OPR6) |
| 384 | |
| 385 | // OPROM reserved (0xdc000-0xdffff) |
| 386 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 387 | Cacheable, ReadWrite, |
| 388 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 389 | 0x00004000,,, OPR7) |
| 390 | |
| 391 | // BIOS Extension (0xe0000-0xe3fff) |
| 392 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 393 | Cacheable, ReadWrite, |
| 394 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 395 | 0x00004000,,, ESG0) |
| 396 | |
| 397 | // BIOS Extension (0xe4000-0xe7fff) |
| 398 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 399 | Cacheable, ReadWrite, |
| 400 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 401 | 0x00004000,,, ESG1) |
| 402 | |
| 403 | // BIOS Extension (0xe8000-0xebfff) |
| 404 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 405 | Cacheable, ReadWrite, |
| 406 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 407 | 0x00004000,,, ESG2) |
| 408 | |
| 409 | // BIOS Extension (0xec000-0xeffff) |
| 410 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 411 | Cacheable, ReadWrite, |
| 412 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 413 | 0x00004000,,, ESG3) |
| 414 | |
| 415 | // System BIOS (0xf0000-0xfffff) |
| 416 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 417 | Cacheable, ReadWrite, |
| 418 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 419 | 0x00010000,,, FSEG) |
| 420 | |
| 421 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
| 422 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 423 | Cacheable, ReadWrite, |
| 424 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 425 | 0x00000000,,, PM01) |
| 426 | |
| 427 | // TPM Area (0xfed40000-0xfed44fff) |
| 428 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 429 | Cacheable, ReadWrite, |
| 430 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 431 | 0x00005000,,, TPMR) |
| 432 | }) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 433 | |
| 434 | Method (_CRS, 0, Serialized) |
| 435 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 436 | // Find PCI resource area in MCRS |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 437 | CreateDwordField(MCRS, ^PM01._MIN, PMIN) |
| 438 | CreateDwordField(MCRS, ^PM01._MAX, PMAX) |
| 439 | CreateDwordField(MCRS, ^PM01._LEN, PLEN) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 440 | |
| 441 | // Fix up PCI memory region |
| 442 | // Start with Top of Lower Usable DRAM |
| 443 | Store (^MCHC.TLUD, Local0) |
| 444 | Store (^MCHC.MEBA, Local1) |
| 445 | |
| 446 | // Check if ME base is equal |
| 447 | If (LEqual (Local0, Local1)) { |
| 448 | // Use Top Of Memory instead |
| 449 | Store (^MCHC.TOM, Local0) |
| 450 | } |
| 451 | |
| 452 | Store (Local0, PMIN) |
Dave Frodin | 2eaa0d4 | 2015-04-23 06:04:46 -0600 | [diff] [blame] | 453 | Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 454 | Add(Subtract(PMAX, PMIN), 1, PLEN) |
| 455 | |
| 456 | Return (MCRS) |
| 457 | } |
| 458 | |
| 459 | /* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ |
| 460 | #include "acpi/haswell_pci_irqs.asl" |