Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | |
| 23 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 24 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 25 | |
| 26 | Name(_ADR, 0) |
| 27 | Name(_BBN, 0) |
| 28 | |
| 29 | Device (MCHC) |
| 30 | { |
| 31 | Name(_ADR, 0x00000000) // 0:0.0 |
| 32 | |
| 33 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 34 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 35 | { |
| 36 | Offset (0x40), // EPBAR |
| 37 | EPEN, 1, // Enable |
| 38 | , 11, // |
| 39 | EPBR, 24, // EPBAR |
| 40 | |
| 41 | Offset (0x48), // MCHBAR |
| 42 | MHEN, 1, // Enable |
| 43 | , 13, // |
| 44 | MHBR, 22, // MCHBAR |
| 45 | |
| 46 | Offset (0x60), // PCIe BAR |
| 47 | PXEN, 1, // Enable |
| 48 | PXSZ, 2, // BAR size |
| 49 | , 23, // |
| 50 | PXBR, 10, // PCIe BAR |
| 51 | |
| 52 | Offset (0x68), // DMIBAR |
| 53 | DMEN, 1, // Enable |
| 54 | , 11, // |
| 55 | DMBR, 24, // DMIBAR |
| 56 | |
| 57 | Offset (0x70), // ME Base Address |
| 58 | MEBA, 64, |
| 59 | |
| 60 | // ... |
| 61 | |
| 62 | Offset (0x80), // PAM0 |
| 63 | , 4, |
| 64 | PM0H, 2, |
| 65 | , 2, |
| 66 | Offset (0x81), // PAM1 |
| 67 | PM1L, 2, |
| 68 | , 2, |
| 69 | PM1H, 2, |
| 70 | , 2, |
| 71 | Offset (0x82), // PAM2 |
| 72 | PM2L, 2, |
| 73 | , 2, |
| 74 | PM2H, 2, |
| 75 | , 2, |
| 76 | Offset (0x83), // PAM3 |
| 77 | PM3L, 2, |
| 78 | , 2, |
| 79 | PM3H, 2, |
| 80 | , 2, |
| 81 | Offset (0x84), // PAM4 |
| 82 | PM4L, 2, |
| 83 | , 2, |
| 84 | PM4H, 2, |
| 85 | , 2, |
| 86 | Offset (0x85), // PAM5 |
| 87 | PM5L, 2, |
| 88 | , 2, |
| 89 | PM5H, 2, |
| 90 | , 2, |
| 91 | Offset (0x86), // PAM6 |
| 92 | PM6L, 2, |
| 93 | , 2, |
| 94 | PM6H, 2, |
| 95 | , 2, |
| 96 | |
| 97 | Offset (0xa0), // Top of Used Memory |
| 98 | TOM, 64, |
| 99 | |
| 100 | Offset (0xbc), // Top of Low Used Memory |
| 101 | TLUD, 32, |
| 102 | } |
| 103 | |
| 104 | Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ |
| 105 | Name (CTCC, 0) /* CTDP Current Selection */ |
| 106 | Name (CTCN, 0) /* CTDP Nominal Select */ |
| 107 | Name (CTCD, 1) /* CTDP Down Select */ |
| 108 | Name (CTCU, 2) /* CTDP Up Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 109 | Name (SPL1, 0) /* Saved PL1 value */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 110 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 111 | OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 112 | Field (MCHB, DWordAcc, Lock, Preserve) |
| 113 | { |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 114 | Offset (0x930), /* PACKAGE_POWER_SKU */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 115 | CTDN, 15, /* CTDP Nominal PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 116 | Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ |
| 117 | PUNI, 4, /* Power Units */ |
| 118 | , 4, |
| 119 | EUNI, 5, /* Energy Units */ |
| 120 | , 3, |
| 121 | TUNI, 4, /* Time Units */ |
| 122 | Offset (0x958), /* PLATFORM_INFO */ |
| 123 | , 40, |
| 124 | LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ |
| 125 | Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 126 | PL1V, 15, /* Power Limit 1 Value */ |
| 127 | PL1E, 1, /* Power Limit 1 Enable */ |
| 128 | PL1C, 1, /* Power Limit 1 Clamp */ |
| 129 | PL1T, 7, /* Power Limit 1 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 130 | Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 131 | PL2V, 15, /* Power Limit 2 Value */ |
| 132 | PL2E, 1, /* Power Limit 2 Enable */ |
| 133 | PL2C, 1, /* Power Limit 2 Clamp */ |
| 134 | PL2T, 7, /* Power Limit 2 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 135 | Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 136 | TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 137 | Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 138 | CTDD, 15, /* CTDP Down PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 139 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 140 | TARD, 8, /* CTDP Down Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 141 | Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 142 | CTDU, 15, /* CTDP Up PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 143 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 144 | TARU, 8, /* CTDP Up Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 145 | Offset (0xf50), /* CONFIG_TDP_CONTROL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 146 | CTCS, 2, /* CTDP Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 147 | Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | TARS, 8, /* Turbo Activation Ratio Select */ |
| 149 | } |
| 150 | |
| 151 | /* |
| 152 | * Search CPU0 _PSS looking for control=arg0 and then |
| 153 | * return previous P-state entry number for new _PPC |
| 154 | * |
| 155 | * Format of _PSS: |
| 156 | * Name (_PSS, Package () { |
| 157 | * Package (6) { freq, power, tlat, blat, control, status } |
| 158 | * } |
| 159 | */ |
| 160 | External (\_PR.CPU0._PSS) |
| 161 | Method (PSSS, 1, NotSerialized) |
| 162 | { |
| 163 | Store (One, Local0) /* Start at P1 */ |
| 164 | Store (SizeOf (\_PR.CPU0._PSS), Local1) |
| 165 | |
| 166 | While (LLess (Local0, Local1)) { |
| 167 | /* Store _PSS entry Control value to Local2 */ |
| 168 | ShiftRight (DeRefOf (Index (DeRefOf (Index |
| 169 | (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2) |
| 170 | If (LEqual (Local2, Arg0)) { |
| 171 | Return (Subtract (Local0, 1)) |
| 172 | } |
| 173 | Increment (Local0) |
| 174 | } |
| 175 | |
| 176 | Return (0) |
| 177 | } |
| 178 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 179 | /* Calculate PL2 based on chip type */ |
| 180 | Method (CPL2, 1, NotSerialized) |
| 181 | { |
| 182 | If (\ISLP ()) { |
| 183 | /* Haswell ULT PL2 = 25W */ |
| 184 | Return (Multiply (25, 8)) |
| 185 | } Else { |
| 186 | /* Haswell Mobile PL2 = 1.25 * PL1 */ |
| 187 | Return (Divide (Multiply (Arg0, 125), 100)) |
| 188 | } |
| 189 | } |
| 190 | |
| 191 | /* Set Config TDP Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 192 | Method (STND, 0, Serialized) |
| 193 | { |
| 194 | If (Acquire (CTCM, 100)) { |
| 195 | Return (0) |
| 196 | } |
| 197 | If (LEqual (CTCD, CTCC)) { |
| 198 | Release (CTCM) |
| 199 | Return (0) |
| 200 | } |
| 201 | |
| 202 | Store ("Set TDP Down", Debug) |
| 203 | |
| 204 | /* Set CTC */ |
| 205 | Store (CTCD, CTCS) |
| 206 | |
| 207 | /* Set TAR */ |
| 208 | Store (TARD, TARS) |
| 209 | |
| 210 | /* Set PPC limit and notify OS */ |
| 211 | Store (PSSS (TARD), PPCM) |
| 212 | PPCN () |
| 213 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 214 | /* Set PL2 */ |
| 215 | Store (CPL2 (CTDD), PL2V) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 216 | |
| 217 | /* Set PL1 */ |
| 218 | Store (CTDD, PL1V) |
| 219 | |
| 220 | /* Store the new TDP Down setting */ |
| 221 | Store (CTCD, CTCC) |
| 222 | |
| 223 | Release (CTCM) |
| 224 | Return (1) |
| 225 | } |
| 226 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 227 | /* Set Config TDP Nominal from Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 228 | Method (STDN, 0, Serialized) |
| 229 | { |
| 230 | If (Acquire (CTCM, 100)) { |
| 231 | Return (0) |
| 232 | } |
| 233 | If (LEqual (CTCN, CTCC)) { |
| 234 | Release (CTCM) |
| 235 | Return (0) |
| 236 | } |
| 237 | |
| 238 | Store ("Set TDP Nominal", Debug) |
| 239 | |
| 240 | /* Set PL1 */ |
| 241 | Store (CTDN, PL1V) |
| 242 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 243 | /* Set PL2 */ |
| 244 | Store (CPL2 (CTDN), PL2V) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 245 | |
| 246 | /* Set PPC limit and notify OS */ |
| 247 | Store (PSSS (TARN), PPCM) |
| 248 | PPCN () |
| 249 | |
| 250 | /* Set TAR */ |
| 251 | Store (TARN, TARS) |
| 252 | |
| 253 | /* Set CTC */ |
| 254 | Store (CTCN, CTCS) |
| 255 | |
| 256 | /* Store the new TDP Nominal setting */ |
| 257 | Store (CTCN, CTCC) |
| 258 | |
| 259 | Release (CTCM) |
| 260 | Return (1) |
| 261 | } |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame^] | 262 | |
| 263 | /* Calculate PL1 value based on requested TDP */ |
| 264 | Method (TDPP, 1, NotSerialized) |
| 265 | { |
| 266 | Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0)) |
| 267 | } |
| 268 | |
| 269 | /* Enable Controllable TDP to limit PL1 to requested value */ |
| 270 | Method (CTLE, 1, Serialized) |
| 271 | { |
| 272 | If (Acquire (CTCM, 100)) { |
| 273 | Return (0) |
| 274 | } |
| 275 | |
| 276 | Store ("Enable PL1 Limit", Debug) |
| 277 | |
| 278 | /* Set _PPC to LFM */ |
| 279 | Store (PSSS (LFM_), Local0) |
| 280 | Add (Local0, 1, PPCM) |
| 281 | \PPCN () |
| 282 | |
| 283 | /* Set TAR to LFM-1 */ |
| 284 | Subtract (LFM_, 1, TARS) |
| 285 | |
| 286 | /* Set PL1 to desired value */ |
| 287 | Store (PL1V, SPL1) |
| 288 | Store (TDPP (Arg0), PL1V) |
| 289 | |
| 290 | /* Set PL1 CLAMP bit */ |
| 291 | Store (One, PL1C) |
| 292 | |
| 293 | Release (CTCM) |
| 294 | Return (1) |
| 295 | } |
| 296 | |
| 297 | /* Disable Controllable TDP */ |
| 298 | Method (CTLD, 0, Serialized) |
| 299 | { |
| 300 | If (Acquire (CTCM, 100)) { |
| 301 | Return (0) |
| 302 | } |
| 303 | |
| 304 | Store ("Disable PL1 Limit", Debug) |
| 305 | |
| 306 | /* Clear PL1 CLAMP bit */ |
| 307 | Store (Zero, PL1C) |
| 308 | |
| 309 | /* Set PL1 to normal value */ |
| 310 | Store (SPL1, PL1V) |
| 311 | |
| 312 | /* Set TAR to 0 */ |
| 313 | Store (Zero, TARS) |
| 314 | |
| 315 | /* Set _PPC to 0 */ |
| 316 | Store (Zero, PPCM) |
| 317 | \PPCN () |
| 318 | |
| 319 | Release (CTCM) |
| 320 | Return (1) |
| 321 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 322 | } |
| 323 | |
| 324 | // Current Resource Settings |
| 325 | |
| 326 | Method (_CRS, 0, Serialized) |
| 327 | { |
| 328 | Name (MCRS, ResourceTemplate() |
| 329 | { |
| 330 | // Bus Numbers |
| 331 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 332 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 333 | |
| 334 | // IO Region 0 |
| 335 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 336 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 337 | |
| 338 | // PCI Config Space |
| 339 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 340 | |
| 341 | // IO Region 1 |
| 342 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 343 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 344 | |
| 345 | // VGA memory (0xa0000-0xbffff) |
| 346 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 347 | Cacheable, ReadWrite, |
| 348 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 349 | 0x00020000,,, ASEG) |
| 350 | |
| 351 | // OPROM reserved (0xc0000-0xc3fff) |
| 352 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 353 | Cacheable, ReadWrite, |
| 354 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 355 | 0x00004000,,, OPR0) |
| 356 | |
| 357 | // OPROM reserved (0xc4000-0xc7fff) |
| 358 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 359 | Cacheable, ReadWrite, |
| 360 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 361 | 0x00004000,,, OPR1) |
| 362 | |
| 363 | // OPROM reserved (0xc8000-0xcbfff) |
| 364 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 365 | Cacheable, ReadWrite, |
| 366 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 367 | 0x00004000,,, OPR2) |
| 368 | |
| 369 | // OPROM reserved (0xcc000-0xcffff) |
| 370 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 371 | Cacheable, ReadWrite, |
| 372 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 373 | 0x00004000,,, OPR3) |
| 374 | |
| 375 | // OPROM reserved (0xd0000-0xd3fff) |
| 376 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 377 | Cacheable, ReadWrite, |
| 378 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 379 | 0x00004000,,, OPR4) |
| 380 | |
| 381 | // OPROM reserved (0xd4000-0xd7fff) |
| 382 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 383 | Cacheable, ReadWrite, |
| 384 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 385 | 0x00004000,,, OPR5) |
| 386 | |
| 387 | // OPROM reserved (0xd8000-0xdbfff) |
| 388 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 389 | Cacheable, ReadWrite, |
| 390 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 391 | 0x00004000,,, OPR6) |
| 392 | |
| 393 | // OPROM reserved (0xdc000-0xdffff) |
| 394 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 395 | Cacheable, ReadWrite, |
| 396 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 397 | 0x00004000,,, OPR7) |
| 398 | |
| 399 | // BIOS Extension (0xe0000-0xe3fff) |
| 400 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 401 | Cacheable, ReadWrite, |
| 402 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 403 | 0x00004000,,, ESG0) |
| 404 | |
| 405 | // BIOS Extension (0xe4000-0xe7fff) |
| 406 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 407 | Cacheable, ReadWrite, |
| 408 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 409 | 0x00004000,,, ESG1) |
| 410 | |
| 411 | // BIOS Extension (0xe8000-0xebfff) |
| 412 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 413 | Cacheable, ReadWrite, |
| 414 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 415 | 0x00004000,,, ESG2) |
| 416 | |
| 417 | // BIOS Extension (0xec000-0xeffff) |
| 418 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 419 | Cacheable, ReadWrite, |
| 420 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 421 | 0x00004000,,, ESG3) |
| 422 | |
| 423 | // System BIOS (0xf0000-0xfffff) |
| 424 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 425 | Cacheable, ReadWrite, |
| 426 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 427 | 0x00010000,,, FSEG) |
| 428 | |
| 429 | // PCI Memory Region (Top of memory-0xfebfffff) |
| 430 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 431 | Cacheable, ReadWrite, |
| 432 | 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, |
| 433 | 0xfec00000,,, PM01) |
| 434 | |
| 435 | // TPM Area (0xfed40000-0xfed44fff) |
| 436 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 437 | Cacheable, ReadWrite, |
| 438 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 439 | 0x00005000,,, TPMR) |
| 440 | }) |
| 441 | |
| 442 | // Find PCI resource area in MCRS |
| 443 | CreateDwordField(MCRS, PM01._MIN, PMIN) |
| 444 | CreateDwordField(MCRS, PM01._MAX, PMAX) |
| 445 | CreateDwordField(MCRS, PM01._LEN, PLEN) |
| 446 | |
| 447 | // Fix up PCI memory region |
| 448 | // Start with Top of Lower Usable DRAM |
| 449 | Store (^MCHC.TLUD, Local0) |
| 450 | Store (^MCHC.MEBA, Local1) |
| 451 | |
| 452 | // Check if ME base is equal |
| 453 | If (LEqual (Local0, Local1)) { |
| 454 | // Use Top Of Memory instead |
| 455 | Store (^MCHC.TOM, Local0) |
| 456 | } |
| 457 | |
| 458 | Store (Local0, PMIN) |
| 459 | Add(Subtract(PMAX, PMIN), 1, PLEN) |
| 460 | |
| 461 | Return (MCRS) |
| 462 | } |
| 463 | |
| 464 | /* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ |
| 465 | #include "acpi/haswell_pci_irqs.asl" |
| 466 | |
| 467 | |