Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 18 | * Foundation, Inc. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | */ |
| 20 | |
| 21 | |
| 22 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 23 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 24 | |
| 25 | Name(_ADR, 0) |
| 26 | Name(_BBN, 0) |
| 27 | |
| 28 | Device (MCHC) |
| 29 | { |
| 30 | Name(_ADR, 0x00000000) // 0:0.0 |
| 31 | |
| 32 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 33 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 34 | { |
| 35 | Offset (0x40), // EPBAR |
| 36 | EPEN, 1, // Enable |
| 37 | , 11, // |
| 38 | EPBR, 24, // EPBAR |
| 39 | |
| 40 | Offset (0x48), // MCHBAR |
| 41 | MHEN, 1, // Enable |
| 42 | , 13, // |
| 43 | MHBR, 22, // MCHBAR |
| 44 | |
| 45 | Offset (0x60), // PCIe BAR |
| 46 | PXEN, 1, // Enable |
| 47 | PXSZ, 2, // BAR size |
| 48 | , 23, // |
| 49 | PXBR, 10, // PCIe BAR |
| 50 | |
| 51 | Offset (0x68), // DMIBAR |
| 52 | DMEN, 1, // Enable |
| 53 | , 11, // |
| 54 | DMBR, 24, // DMIBAR |
| 55 | |
| 56 | Offset (0x70), // ME Base Address |
| 57 | MEBA, 64, |
| 58 | |
| 59 | // ... |
| 60 | |
| 61 | Offset (0x80), // PAM0 |
| 62 | , 4, |
| 63 | PM0H, 2, |
| 64 | , 2, |
| 65 | Offset (0x81), // PAM1 |
| 66 | PM1L, 2, |
| 67 | , 2, |
| 68 | PM1H, 2, |
| 69 | , 2, |
| 70 | Offset (0x82), // PAM2 |
| 71 | PM2L, 2, |
| 72 | , 2, |
| 73 | PM2H, 2, |
| 74 | , 2, |
| 75 | Offset (0x83), // PAM3 |
| 76 | PM3L, 2, |
| 77 | , 2, |
| 78 | PM3H, 2, |
| 79 | , 2, |
| 80 | Offset (0x84), // PAM4 |
| 81 | PM4L, 2, |
| 82 | , 2, |
| 83 | PM4H, 2, |
| 84 | , 2, |
| 85 | Offset (0x85), // PAM5 |
| 86 | PM5L, 2, |
| 87 | , 2, |
| 88 | PM5H, 2, |
| 89 | , 2, |
| 90 | Offset (0x86), // PAM6 |
| 91 | PM6L, 2, |
| 92 | , 2, |
| 93 | PM6H, 2, |
| 94 | , 2, |
| 95 | |
| 96 | Offset (0xa0), // Top of Used Memory |
| 97 | TOM, 64, |
| 98 | |
| 99 | Offset (0xbc), // Top of Low Used Memory |
| 100 | TLUD, 32, |
| 101 | } |
| 102 | |
| 103 | Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ |
| 104 | Name (CTCC, 0) /* CTDP Current Selection */ |
| 105 | Name (CTCN, 0) /* CTDP Nominal Select */ |
| 106 | Name (CTCD, 1) /* CTDP Down Select */ |
| 107 | Name (CTCU, 2) /* CTDP Up Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 108 | Name (SPL1, 0) /* Saved PL1 value */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 109 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 110 | OperationRegion (MCHB, SystemMemory, Add(DEFAULT_MCHBAR,0x5000), 0x1000) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 111 | Field (MCHB, DWordAcc, Lock, Preserve) |
| 112 | { |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 113 | Offset (0x930), /* PACKAGE_POWER_SKU */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 114 | CTDN, 15, /* CTDP Nominal PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 115 | Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ |
| 116 | PUNI, 4, /* Power Units */ |
| 117 | , 4, |
| 118 | EUNI, 5, /* Energy Units */ |
| 119 | , 3, |
| 120 | TUNI, 4, /* Time Units */ |
| 121 | Offset (0x958), /* PLATFORM_INFO */ |
| 122 | , 40, |
| 123 | LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ |
| 124 | Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 125 | PL1V, 15, /* Power Limit 1 Value */ |
| 126 | PL1E, 1, /* Power Limit 1 Enable */ |
| 127 | PL1C, 1, /* Power Limit 1 Clamp */ |
| 128 | PL1T, 7, /* Power Limit 1 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 129 | Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 130 | PL2V, 15, /* Power Limit 2 Value */ |
| 131 | PL2E, 1, /* Power Limit 2 Enable */ |
| 132 | PL2C, 1, /* Power Limit 2 Clamp */ |
| 133 | PL2T, 7, /* Power Limit 2 Time */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 134 | Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 136 | Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 137 | CTDD, 15, /* CTDP Down PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 138 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 139 | TARD, 8, /* CTDP Down Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 140 | Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 141 | CTDU, 15, /* CTDP Up PL1 */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 142 | , 1, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 143 | TARU, 8, /* CTDP Up Turbo Activation Ratio */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 144 | Offset (0xf50), /* CONFIG_TDP_CONTROL */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 145 | CTCS, 2, /* CTDP Select */ |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 146 | Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 147 | TARS, 8, /* Turbo Activation Ratio Select */ |
| 148 | } |
| 149 | |
| 150 | /* |
| 151 | * Search CPU0 _PSS looking for control=arg0 and then |
| 152 | * return previous P-state entry number for new _PPC |
| 153 | * |
| 154 | * Format of _PSS: |
| 155 | * Name (_PSS, Package () { |
| 156 | * Package (6) { freq, power, tlat, blat, control, status } |
| 157 | * } |
| 158 | */ |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 159 | External (\_PR.CP00._PSS) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 160 | Method (PSSS, 1, NotSerialized) |
| 161 | { |
| 162 | Store (One, Local0) /* Start at P1 */ |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 163 | Store (SizeOf (\_PR.CP00._PSS), Local1) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 164 | |
| 165 | While (LLess (Local0, Local1)) { |
| 166 | /* Store _PSS entry Control value to Local2 */ |
| 167 | ShiftRight (DeRefOf (Index (DeRefOf (Index |
Timothy Pearson | 033bb4b | 2015-02-10 22:21:39 -0600 | [diff] [blame] | 168 | (\_PR.CP00._PSS, Local0)), 4)), 8, Local2) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 169 | If (LEqual (Local2, Arg0)) { |
| 170 | Return (Subtract (Local0, 1)) |
| 171 | } |
| 172 | Increment (Local0) |
| 173 | } |
| 174 | |
| 175 | Return (0) |
| 176 | } |
| 177 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 178 | /* Calculate PL2 based on chip type */ |
| 179 | Method (CPL2, 1, NotSerialized) |
| 180 | { |
| 181 | If (\ISLP ()) { |
| 182 | /* Haswell ULT PL2 = 25W */ |
| 183 | Return (Multiply (25, 8)) |
| 184 | } Else { |
| 185 | /* Haswell Mobile PL2 = 1.25 * PL1 */ |
| 186 | Return (Divide (Multiply (Arg0, 125), 100)) |
| 187 | } |
| 188 | } |
| 189 | |
| 190 | /* Set Config TDP Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 191 | Method (STND, 0, Serialized) |
| 192 | { |
| 193 | If (Acquire (CTCM, 100)) { |
| 194 | Return (0) |
| 195 | } |
| 196 | If (LEqual (CTCD, CTCC)) { |
| 197 | Release (CTCM) |
| 198 | Return (0) |
| 199 | } |
| 200 | |
| 201 | Store ("Set TDP Down", Debug) |
| 202 | |
| 203 | /* Set CTC */ |
| 204 | Store (CTCD, CTCS) |
| 205 | |
| 206 | /* Set TAR */ |
| 207 | Store (TARD, TARS) |
| 208 | |
| 209 | /* Set PPC limit and notify OS */ |
| 210 | Store (PSSS (TARD), PPCM) |
| 211 | PPCN () |
| 212 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 213 | /* Set PL2 */ |
| 214 | Store (CPL2 (CTDD), PL2V) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 215 | |
| 216 | /* Set PL1 */ |
| 217 | Store (CTDD, PL1V) |
| 218 | |
| 219 | /* Store the new TDP Down setting */ |
| 220 | Store (CTCD, CTCC) |
| 221 | |
| 222 | Release (CTCM) |
| 223 | Return (1) |
| 224 | } |
| 225 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 226 | /* Set Config TDP Nominal from Down */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 227 | Method (STDN, 0, Serialized) |
| 228 | { |
| 229 | If (Acquire (CTCM, 100)) { |
| 230 | Return (0) |
| 231 | } |
| 232 | If (LEqual (CTCN, CTCC)) { |
| 233 | Release (CTCM) |
| 234 | Return (0) |
| 235 | } |
| 236 | |
| 237 | Store ("Set TDP Nominal", Debug) |
| 238 | |
| 239 | /* Set PL1 */ |
| 240 | Store (CTDN, PL1V) |
| 241 | |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 242 | /* Set PL2 */ |
| 243 | Store (CPL2 (CTDN), PL2V) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 244 | |
| 245 | /* Set PPC limit and notify OS */ |
| 246 | Store (PSSS (TARN), PPCM) |
| 247 | PPCN () |
| 248 | |
| 249 | /* Set TAR */ |
| 250 | Store (TARN, TARS) |
| 251 | |
| 252 | /* Set CTC */ |
| 253 | Store (CTCN, CTCS) |
| 254 | |
| 255 | /* Store the new TDP Nominal setting */ |
| 256 | Store (CTCN, CTCC) |
| 257 | |
| 258 | Release (CTCM) |
| 259 | Return (1) |
| 260 | } |
Duncan Laurie | b171179 | 2013-06-28 16:01:53 -0700 | [diff] [blame] | 261 | |
| 262 | /* Calculate PL1 value based on requested TDP */ |
| 263 | Method (TDPP, 1, NotSerialized) |
| 264 | { |
| 265 | Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0)) |
| 266 | } |
| 267 | |
| 268 | /* Enable Controllable TDP to limit PL1 to requested value */ |
| 269 | Method (CTLE, 1, Serialized) |
| 270 | { |
| 271 | If (Acquire (CTCM, 100)) { |
| 272 | Return (0) |
| 273 | } |
| 274 | |
| 275 | Store ("Enable PL1 Limit", Debug) |
| 276 | |
| 277 | /* Set _PPC to LFM */ |
| 278 | Store (PSSS (LFM_), Local0) |
| 279 | Add (Local0, 1, PPCM) |
| 280 | \PPCN () |
| 281 | |
| 282 | /* Set TAR to LFM-1 */ |
| 283 | Subtract (LFM_, 1, TARS) |
| 284 | |
| 285 | /* Set PL1 to desired value */ |
| 286 | Store (PL1V, SPL1) |
| 287 | Store (TDPP (Arg0), PL1V) |
| 288 | |
| 289 | /* Set PL1 CLAMP bit */ |
| 290 | Store (One, PL1C) |
| 291 | |
| 292 | Release (CTCM) |
| 293 | Return (1) |
| 294 | } |
| 295 | |
| 296 | /* Disable Controllable TDP */ |
| 297 | Method (CTLD, 0, Serialized) |
| 298 | { |
| 299 | If (Acquire (CTCM, 100)) { |
| 300 | Return (0) |
| 301 | } |
| 302 | |
| 303 | Store ("Disable PL1 Limit", Debug) |
| 304 | |
| 305 | /* Clear PL1 CLAMP bit */ |
| 306 | Store (Zero, PL1C) |
| 307 | |
| 308 | /* Set PL1 to normal value */ |
| 309 | Store (SPL1, PL1V) |
| 310 | |
| 311 | /* Set TAR to 0 */ |
| 312 | Store (Zero, TARS) |
| 313 | |
| 314 | /* Set _PPC to 0 */ |
| 315 | Store (Zero, PPCM) |
| 316 | \PPCN () |
| 317 | |
| 318 | Release (CTCM) |
| 319 | Return (1) |
| 320 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 321 | } |
| 322 | |
| 323 | // Current Resource Settings |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame^] | 324 | Name (MCRS, ResourceTemplate() |
| 325 | { |
| 326 | // Bus Numbers |
| 327 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 328 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 329 | |
| 330 | // IO Region 0 |
| 331 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 332 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 333 | |
| 334 | // PCI Config Space |
| 335 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 336 | |
| 337 | // IO Region 1 |
| 338 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 339 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 340 | |
| 341 | // VGA memory (0xa0000-0xbffff) |
| 342 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 343 | Cacheable, ReadWrite, |
| 344 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 345 | 0x00020000,,, ASEG) |
| 346 | |
| 347 | // OPROM reserved (0xc0000-0xc3fff) |
| 348 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 349 | Cacheable, ReadWrite, |
| 350 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 351 | 0x00004000,,, OPR0) |
| 352 | |
| 353 | // OPROM reserved (0xc4000-0xc7fff) |
| 354 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 355 | Cacheable, ReadWrite, |
| 356 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 357 | 0x00004000,,, OPR1) |
| 358 | |
| 359 | // OPROM reserved (0xc8000-0xcbfff) |
| 360 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 361 | Cacheable, ReadWrite, |
| 362 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 363 | 0x00004000,,, OPR2) |
| 364 | |
| 365 | // OPROM reserved (0xcc000-0xcffff) |
| 366 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 367 | Cacheable, ReadWrite, |
| 368 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 369 | 0x00004000,,, OPR3) |
| 370 | |
| 371 | // OPROM reserved (0xd0000-0xd3fff) |
| 372 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 373 | Cacheable, ReadWrite, |
| 374 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 375 | 0x00004000,,, OPR4) |
| 376 | |
| 377 | // OPROM reserved (0xd4000-0xd7fff) |
| 378 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 379 | Cacheable, ReadWrite, |
| 380 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 381 | 0x00004000,,, OPR5) |
| 382 | |
| 383 | // OPROM reserved (0xd8000-0xdbfff) |
| 384 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 385 | Cacheable, ReadWrite, |
| 386 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 387 | 0x00004000,,, OPR6) |
| 388 | |
| 389 | // OPROM reserved (0xdc000-0xdffff) |
| 390 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 391 | Cacheable, ReadWrite, |
| 392 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 393 | 0x00004000,,, OPR7) |
| 394 | |
| 395 | // BIOS Extension (0xe0000-0xe3fff) |
| 396 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 397 | Cacheable, ReadWrite, |
| 398 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 399 | 0x00004000,,, ESG0) |
| 400 | |
| 401 | // BIOS Extension (0xe4000-0xe7fff) |
| 402 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 403 | Cacheable, ReadWrite, |
| 404 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 405 | 0x00004000,,, ESG1) |
| 406 | |
| 407 | // BIOS Extension (0xe8000-0xebfff) |
| 408 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 409 | Cacheable, ReadWrite, |
| 410 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 411 | 0x00004000,,, ESG2) |
| 412 | |
| 413 | // BIOS Extension (0xec000-0xeffff) |
| 414 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 415 | Cacheable, ReadWrite, |
| 416 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 417 | 0x00004000,,, ESG3) |
| 418 | |
| 419 | // System BIOS (0xf0000-0xfffff) |
| 420 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 421 | Cacheable, ReadWrite, |
| 422 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 423 | 0x00010000,,, FSEG) |
| 424 | |
| 425 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
| 426 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 427 | Cacheable, ReadWrite, |
| 428 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 429 | 0x00000000,,, PM01) |
| 430 | |
| 431 | // TPM Area (0xfed40000-0xfed44fff) |
| 432 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 433 | Cacheable, ReadWrite, |
| 434 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 435 | 0x00005000,,, TPMR) |
| 436 | }) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 437 | |
| 438 | Method (_CRS, 0, Serialized) |
| 439 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 440 | // Find PCI resource area in MCRS |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame^] | 441 | CreateDwordField(MCRS, ^PM01._MIN, PMIN) |
| 442 | CreateDwordField(MCRS, ^PM01._MAX, PMAX) |
| 443 | CreateDwordField(MCRS, ^PM01._LEN, PLEN) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 444 | |
| 445 | // Fix up PCI memory region |
| 446 | // Start with Top of Lower Usable DRAM |
| 447 | Store (^MCHC.TLUD, Local0) |
| 448 | Store (^MCHC.MEBA, Local1) |
| 449 | |
| 450 | // Check if ME base is equal |
| 451 | If (LEqual (Local0, Local1)) { |
| 452 | // Use Top Of Memory instead |
| 453 | Store (^MCHC.TOM, Local0) |
| 454 | } |
| 455 | |
| 456 | Store (Local0, PMIN) |
Dave Frodin | 2eaa0d4 | 2015-04-23 06:04:46 -0600 | [diff] [blame] | 457 | Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 458 | Add(Subtract(PMAX, PMIN), 1, PLEN) |
| 459 | |
| 460 | Return (MCRS) |
| 461 | } |
| 462 | |
| 463 | /* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ |
| 464 | #include "acpi/haswell_pci_irqs.asl" |