Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 1 | chip soc/intel/apollolake |
| 2 | |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 3 | register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 4 | # Disable unused clkreq of PCIe root ports |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 5 | register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" |
| 6 | register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" |
| 7 | register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" |
| 8 | register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" |
| 9 | register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 10 | |
| 11 | # GPIO for PERST_0 |
| 12 | # If the Board has PERST_0 signal, assign the GPIO |
| 13 | # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF |
Kevin Chiu | f5fb219 | 2016-11-09 13:48:12 +0800 | [diff] [blame] | 14 | register "prt0_gpio" = "GPIO_122" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 15 | |
Venkateswarlu Vinjamuri | 7e4d12c | 2017-02-24 15:54:39 -0800 | [diff] [blame] | 16 | # GPIO for SD card detect |
| 17 | register "sdcard_cd_gpio" = "GPIO_177" |
| 18 | |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 19 | # EMMC TX DATA Delay 1 |
| 20 | # Refer to EDS-Vol2-22.3. |
| 21 | # [14:8] steps of delay for HS400, each 125ps. |
| 22 | # [6:0] steps of delay for SDR104/HS200, each 125ps. |
| 23 | register "emmc_tx_data_cntl1" = "0x0C16" |
| 24 | |
| 25 | # EMMC TX DATA Delay 2 |
| 26 | # Refer to EDS-Vol2-22.3. |
| 27 | # [30:24] steps of delay for SDR50, each 125ps. |
| 28 | # [22:16] steps of delay for DDR50, each 125ps. |
| 29 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 30 | # [6:0] steps of delay for SDR12, each 125ps. |
| 31 | register "emmc_tx_data_cntl2" = "0x28162828" |
| 32 | |
| 33 | # EMMC RX CMD/DATA Delay 1 |
| 34 | # Refer to EDS-Vol2-22.3. |
| 35 | # [30:24] steps of delay for SDR50, each 125ps. |
| 36 | # [22:16] steps of delay for DDR50, each 125ps. |
| 37 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 38 | # [6:0] steps of delay for SDR12, each 125ps. |
| 39 | register "emmc_rx_cmd_data_cntl1" = "0x00181717" |
| 40 | |
| 41 | # EMMC RX CMD/DATA Delay 2 |
| 42 | # Refer to EDS-Vol2-22.3. |
| 43 | # [17:16] stands for Rx Clock before Output Buffer |
| 44 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps. |
| 45 | # [6:0] steps of delay for HS200, each 125ps. |
| 46 | register "emmc_rx_cmd_data_cntl2" = "0x10008" |
| 47 | |
| 48 | # Enable DPTF |
| 49 | register "dptf_enable" = "1" |
| 50 | |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 51 | # PL1 override 12 W: the energy calculation is wrong with the |
Kevin Chiu | c4943d8 | 2016-11-09 14:07:30 +0800 | [diff] [blame] | 52 | # current VR solution. Experiments show that SoC TDP max (6W) can |
| 53 | # be reached when RAPL PL1 is set to 12W. |
Kevin Chiu | a0f6f9b | 2016-12-09 11:42:05 +0800 | [diff] [blame] | 54 | # Set RAPL PL2 to 15W. |
Sumeet R Pawnikar | 2adb50d | 2020-05-09 15:37:09 +0530 | [diff] [blame] | 55 | register "power_limits_config" = "{ |
| 56 | .tdp_pl1_override = 12, |
| 57 | .tdp_pl2_override = 15, |
| 58 | }" |
Kevin Chiu | c4943d8 | 2016-11-09 14:07:30 +0800 | [diff] [blame] | 59 | |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 60 | # Enable Audio Clock and Power gating |
| 61 | register "hdaudio_clk_gate_enable" = "1" |
| 62 | register "hdaudio_pwr_gate_enable" = "1" |
| 63 | register "hdaudio_bios_config_lockdown" = "1" |
| 64 | |
| 65 | # Enable lpss s0ix |
| 66 | register "lpss_s0ix_enable" = "1" |
| 67 | |
| 68 | # GPE configuration |
| 69 | # Note that GPE events called out in ASL code rely on this |
| 70 | # route, i.e., if this route changes then the affected GPE |
| 71 | # offset bits also need to be changed. This sets the PMC register |
| 72 | # GPE_CFG fields. |
| 73 | register "gpe0_dw1" = "PMC_GPE_N_31_0" |
| 74 | register "gpe0_dw2" = "PMC_GPE_N_63_32" |
| 75 | register "gpe0_dw3" = "PMC_GPE_SW_31_0" |
| 76 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 77 | # Intel Common SoC Config |
| 78 | #+-------------------+---------------------------+ |
| 79 | #| Field | Value | |
| 80 | #+-------------------+---------------------------+ |
| 81 | #| I2C0 | Audio | |
| 82 | #| I2C2 | TPM | |
| 83 | #| I2C3 | Touchscreen | |
| 84 | #| I2C4 | Trackpad | |
| 85 | #+-------------------+---------------------------+ |
| 86 | register "common_soc_config" = "{ |
| 87 | .i2c[0] = { |
| 88 | .speed = I2C_SPEED_FAST, |
| 89 | .rise_time_ns = 104, |
| 90 | .fall_time_ns = 52, |
| 91 | }, |
| 92 | .i2c[2] = { |
| 93 | .early_init = 1, |
| 94 | .speed = I2C_SPEED_FAST, |
| 95 | .rise_time_ns = 50, |
| 96 | .fall_time_ns = 23, |
| 97 | }, |
| 98 | .i2c[3] = { |
| 99 | .speed = I2C_SPEED_FAST, |
| 100 | .rise_time_ns = 76, |
| 101 | .fall_time_ns = 164, |
| 102 | }, |
| 103 | .i2c[4] = { |
| 104 | .speed = I2C_SPEED_FAST, |
| 105 | .rise_time_ns = 90, |
| 106 | .fall_time_ns = 164, |
| 107 | }, |
Kevin Chiu | 961d6d4 | 2016-11-09 09:52:55 +0800 | [diff] [blame] | 108 | }" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 109 | |
| 110 | # Minimum SLP S3 assertion width 28ms. |
| 111 | register "slp_s3_assertion_width_usecs" = "28000" |
| 112 | |
Kevin Chiu | 0117924 | 2017-01-25 23:06:23 +0800 | [diff] [blame] | 113 | # Override USB2 PER PORT register (PORT 0) |
| 114 | register "usb2eye[0]" = "{ |
| 115 | .Usb20PerPortPeTxiSet = 7, |
| 116 | .Usb20PerPortTxiSet = 1, |
| 117 | .Usb20IUsbTxEmphasisEn = 3, |
| 118 | .Usb20PerPortTxPeHalf = 0, |
| 119 | }" |
| 120 | |
| 121 | # Override USB2 PER PORT register (PORT 1) |
| 122 | register "usb2eye[1]" = "{ |
| 123 | .Usb20PerPortPeTxiSet = 7, |
| 124 | .Usb20PerPortTxiSet = 2, |
| 125 | .Usb20IUsbTxEmphasisEn = 3, |
| 126 | .Usb20PerPortTxPeHalf = 0, |
| 127 | }" |
| 128 | |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 129 | device domain 0 on |
| 130 | device pci 00.0 on end # - Host Bridge |
| 131 | device pci 00.1 on end # - DPTF |
Matt DeVillier | d095fd8 | 2023-04-30 16:59:17 -0500 | [diff] [blame] | 132 | device pci 00.2 off end # - NPK |
Matt DeVillier | 2ece212 | 2020-04-30 10:55:32 -0500 | [diff] [blame] | 133 | device pci 02.0 on # - Gen |
| 134 | register "gfx" = "GMA_DEFAULT_PANEL(0)" |
| 135 | end |
Matt DeVillier | 5f662e9 | 2022-02-13 13:20:17 -0600 | [diff] [blame] | 136 | device pci 03.0 off end # - Iunit |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 137 | device pci 0d.0 on end # - P2SB |
| 138 | device pci 0d.1 on end # - PMC |
| 139 | device pci 0d.2 on end # - SPI |
| 140 | device pci 0d.3 on end # - Shared SRAM |
| 141 | device pci 0e.0 on # - Audio |
| 142 | chip drivers/generic/max98357a |
Aamir Bohra | a1c82c5 | 2020-03-16 18:57:48 +0530 | [diff] [blame] | 143 | register "hid" = ""MX98357A"" |
Martin Roth | 2e6aeba | 2016-10-07 10:48:31 -0600 | [diff] [blame] | 144 | register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" |
Kevin Chiu | 49ef5aa | 2016-11-09 14:23:06 +0800 | [diff] [blame] | 145 | register "sdmode_delay" = "5" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 146 | device generic 0 on end |
| 147 | end |
| 148 | end |
Subrata Banik | e9b9373 | 2020-09-17 15:48:54 +0530 | [diff] [blame] | 149 | device pci 0f.0 on end # - CSE |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 150 | device pci 11.0 off end # - ISH |
| 151 | device pci 12.0 off end # - SATA |
| 152 | device pci 13.0 off end # - Root Port 2 - PCIe-A 0 |
| 153 | device pci 13.1 off end # - Root Port 3 - PCIe-A 1 |
| 154 | device pci 13.2 off end # - Root Port 4 - PCIe-A 2 |
| 155 | device pci 13.3 off end # - Root Port 5 - PCIe-A 3 |
| 156 | device pci 14.0 on |
Furquan Shaikh | a266d1e | 2020-10-04 12:52:54 -0700 | [diff] [blame] | 157 | chip drivers/wifi/generic |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 158 | register "wake" = "GPE0_DW3_00" |
| 159 | device pci 00.0 on end |
| 160 | end |
| 161 | end # - Root Port 0 - PCIe-B 0 - Wifi |
| 162 | device pci 14.1 off end # - Root Port 1 - PCIe-B 1 |
| 163 | device pci 15.0 on end # - XHCI |
| 164 | device pci 15.1 off end # - XDCI |
| 165 | device pci 16.0 on # - I2C 0 |
| 166 | chip drivers/i2c/da7219 |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 167 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 168 | register "btn_cfg" = "50" |
Terry Cheong | 053c901 | 2023-12-12 11:04:33 +0800 | [diff] [blame^] | 169 | register "mic_det_thr" = "200" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 170 | register "jack_ins_deb" = "20" |
| 171 | register "jack_det_rate" = ""32ms_64ms"" |
| 172 | register "jack_rem_deb" = "1" |
| 173 | register "a_d_btn_thr" = "0xa" |
| 174 | register "d_b_btn_thr" = "0x16" |
| 175 | register "b_c_btn_thr" = "0x21" |
| 176 | register "c_mic_btn_thr" = "0x3e" |
| 177 | register "btn_avg" = "4" |
| 178 | register "adc_1bit_rpt" = "1" |
| 179 | register "micbias_lvl" = "2600" |
| 180 | register "mic_amp_in_sel" = ""diff"" |
| 181 | device i2c 1a on end |
| 182 | end |
| 183 | end |
| 184 | device pci 16.1 on end # - I2C 1 |
| 185 | device pci 16.2 on |
| 186 | chip drivers/i2c/tpm |
| 187 | register "hid" = ""GOOG0005"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 188 | register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 189 | device i2c 50 on end |
| 190 | end |
| 191 | end # - I2C 2 |
| 192 | device pci 16.3 on |
Furquan Shaikh | 5360c7e | 2017-02-19 01:18:09 -0800 | [diff] [blame] | 193 | chip drivers/i2c/hid |
| 194 | register "generic.hid" = ""WCOMNTN2"" |
| 195 | register "generic.desc" = ""WCOM Touchscreen"" |
Furquan Shaikh | 5b9b593 | 2017-02-21 13:16:30 -0800 | [diff] [blame] | 196 | register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" |
Matt DeVillier | a0e32aa | 2022-12-20 16:33:12 -0600 | [diff] [blame] | 197 | register "generic.detect" = "1" |
Furquan Shaikh | 5360c7e | 2017-02-19 01:18:09 -0800 | [diff] [blame] | 198 | register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" |
| 199 | register "generic.reset_delay_ms" = "20" |
| 200 | register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" |
| 201 | register "generic.enable_delay_ms" = "1" |
| 202 | register "generic.has_power_resource" = "1" |
Furquan Shaikh | 8be4fdf | 2016-10-21 16:45:59 -0700 | [diff] [blame] | 203 | register "hid_desc_reg_offset" = "0x1" |
| 204 | device i2c 0xA on end |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 205 | end |
Kevin Chiu | 5aadea9 | 2017-01-10 22:31:05 +0800 | [diff] [blame] | 206 | chip drivers/i2c/generic |
| 207 | register "hid" = ""ELAN0001"" |
| 208 | register "desc" = ""ELAN Touchscreen"" |
Matt DeVillier | 48894ea | 2022-12-20 16:31:51 -0600 | [diff] [blame] | 209 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_21_IRQ)" |
Matt DeVillier | a0e32aa | 2022-12-20 16:33:12 -0600 | [diff] [blame] | 210 | register "detect" = "1" |
Furquan Shaikh | a7a517d | 2017-01-25 19:15:49 -0800 | [diff] [blame] | 211 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" |
| 212 | register "reset_delay_ms" = "20" |
| 213 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" |
| 214 | register "enable_delay_ms" = "1" |
| 215 | register "has_power_resource" = "1" |
Kevin Chiu | 5aadea9 | 2017-01-10 22:31:05 +0800 | [diff] [blame] | 216 | device i2c 10 on end |
| 217 | end |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 218 | end # - I2C 3 |
| 219 | device pci 17.0 on |
| 220 | chip drivers/i2c/generic |
| 221 | register "hid" = ""ELAN0000"" |
| 222 | register "desc" = ""ELAN Touchpad"" |
Matt DeVillier | 48894ea | 2022-12-20 16:31:51 -0600 | [diff] [blame] | 223 | register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_18_IRQ)" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 224 | register "wake" = "GPE0_DW1_15" |
Matt DeVillier | 2cf52d8 | 2022-09-01 15:09:24 -0500 | [diff] [blame] | 225 | register "detect" = "1" |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 226 | device i2c 15 on end |
| 227 | end |
| 228 | end # - I2C 4 |
Kevin Chiu | ca38753 | 2016-11-23 18:06:39 +0800 | [diff] [blame] | 229 | device pci 17.1 off end # - I2C 5 |
| 230 | device pci 17.2 off end # - I2C 6 |
| 231 | device pci 17.3 off end # - I2C 7 |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 232 | device pci 18.0 on end # - UART 0 |
| 233 | device pci 18.1 on end # - UART 1 |
| 234 | device pci 18.2 on end # - UART 2 |
Kevin Chiu | ca38753 | 2016-11-23 18:06:39 +0800 | [diff] [blame] | 235 | device pci 18.3 off end # - UART 3 |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 236 | device pci 19.0 on end # - SPI 0 |
Kevin Chiu | ca38753 | 2016-11-23 18:06:39 +0800 | [diff] [blame] | 237 | device pci 19.1 off end # - SPI 1 |
| 238 | device pci 19.2 off end # - SPI 2 |
Kevin Chiu | 0b1a90d | 2016-10-03 17:15:15 +0800 | [diff] [blame] | 239 | device pci 1a.0 on end # - PWM |
| 240 | device pci 1b.0 on end # - SDCARD |
| 241 | device pci 1c.0 on end # - eMMC |
| 242 | device pci 1e.0 off end # - SDIO |
| 243 | device pci 1f.0 on # - LPC |
| 244 | chip ec/google/chromeec |
| 245 | device pnp 0c09.0 on end |
| 246 | end |
| 247 | end |
| 248 | device pci 1f.1 on end # - SMBUS |
| 249 | end |
| 250 | end |