blob: da893b1d3699f099297247bf680b7b33283daabe [file] [log] [blame]
Kevin Chiu0b1a90d2016-10-03 17:15:15 +08001chip soc/intel/apollolake
2
3 device cpu_cluster 0 on
4 device lapic 0 on end
5 end
6
7 register "pcie_rp0_clkreq_pin" = "0" # wifi/bt
8 # Disable unused clkreq of PCIe root ports
9 register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
10 register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
11 register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
12 register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
13 register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
14
15 # GPIO for PERST_0
16 # If the Board has PERST_0 signal, assign the GPIO
17 # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
Kevin Chiuf5fb2192016-11-09 13:48:12 +080018 register "prt0_gpio" = "GPIO_122"
Kevin Chiu0b1a90d2016-10-03 17:15:15 +080019
20 # EMMC TX DATA Delay 1
21 # Refer to EDS-Vol2-22.3.
22 # [14:8] steps of delay for HS400, each 125ps.
23 # [6:0] steps of delay for SDR104/HS200, each 125ps.
24 register "emmc_tx_data_cntl1" = "0x0C16"
25
26 # EMMC TX DATA Delay 2
27 # Refer to EDS-Vol2-22.3.
28 # [30:24] steps of delay for SDR50, each 125ps.
29 # [22:16] steps of delay for DDR50, each 125ps.
30 # [14:8] steps of delay for SDR25/HS50, each 125ps.
31 # [6:0] steps of delay for SDR12, each 125ps.
32 register "emmc_tx_data_cntl2" = "0x28162828"
33
34 # EMMC RX CMD/DATA Delay 1
35 # Refer to EDS-Vol2-22.3.
36 # [30:24] steps of delay for SDR50, each 125ps.
37 # [22:16] steps of delay for DDR50, each 125ps.
38 # [14:8] steps of delay for SDR25/HS50, each 125ps.
39 # [6:0] steps of delay for SDR12, each 125ps.
40 register "emmc_rx_cmd_data_cntl1" = "0x00181717"
41
42 # EMMC RX CMD/DATA Delay 2
43 # Refer to EDS-Vol2-22.3.
44 # [17:16] stands for Rx Clock before Output Buffer
45 # [14:8] steps of delay for Auto Tuning Mode, each 125ps.
46 # [6:0] steps of delay for HS200, each 125ps.
47 register "emmc_rx_cmd_data_cntl2" = "0x10008"
48
49 # Enable DPTF
50 register "dptf_enable" = "1"
51
Kevin Chiuc4943d82016-11-09 14:07:30 +080052 # PL1 override 12000 mW: the energy calculation is wrong with the
53 # current VR solution. Experiments show that SoC TDP max (6W) can
54 # be reached when RAPL PL1 is set to 12W.
55 register "tdp_pl1_override_mw" = "12000"
56
Kevin Chiu0b1a90d2016-10-03 17:15:15 +080057 # Enable Audio Clock and Power gating
58 register "hdaudio_clk_gate_enable" = "1"
59 register "hdaudio_pwr_gate_enable" = "1"
60 register "hdaudio_bios_config_lockdown" = "1"
61
62 # Enable lpss s0ix
63 register "lpss_s0ix_enable" = "1"
64
65 # GPE configuration
66 # Note that GPE events called out in ASL code rely on this
67 # route, i.e., if this route changes then the affected GPE
68 # offset bits also need to be changed. This sets the PMC register
69 # GPE_CFG fields.
70 register "gpe0_dw1" = "PMC_GPE_N_31_0"
71 register "gpe0_dw2" = "PMC_GPE_N_63_32"
72 register "gpe0_dw3" = "PMC_GPE_SW_31_0"
73
Kevin Chiu961d6d42016-11-09 09:52:55 +080074 # Limit I2C0 Audio codec da7219 speed to 400kHz with manually tuned values.
75 register "i2c[0]" = "{
76 .speed = I2C_SPEED_FAST,
77 .speed_config[0] = {
78 .speed = I2C_SPEED_FAST,
79 .scl_lcnt = 0xd0,
80 .scl_hcnt = 0x68,
81 .sda_hold = 0x27,
82 }
83 }"
84
85 # Enable I2C2 bus early for TPM access and configure as 400kHz
86 # with manually tuned values.
87 register "i2c[2]" = "{
88 .early_init = 1,
89 .speed = I2C_SPEED_FAST,
90 .speed_config[0] = {
91 .speed = I2C_SPEED_FAST,
92 .scl_lcnt = 0xd0,
93 .scl_hcnt = 0x68,
94 .sda_hold = 0x27,
95 }
96 }"
97
98 # Limit I2C3 WACOM touchscreen speed to 400kHz with manually tuned values.
99 register "i2c[3]" = "{
100 .speed = I2C_SPEED_FAST,
101 .speed_config[0] = {
102 .speed = I2C_SPEED_FAST,
103 .scl_lcnt = 0xd0,
104 .scl_hcnt = 0x68,
105 .sda_hold = 0x27,
106 }
107 }"
108
109 # Limit trackpad speed to 400kHz with manually tuned values.
110 register "i2c[4]" = "{
111 .speed = I2C_SPEED_FAST,
112 .speed_config[0] = {
113 .speed = I2C_SPEED_FAST,
114 .scl_lcnt = 0xd0,
115 .scl_hcnt = 0x68,
116 .sda_hold = 0x27,
117 }
118 }"
Kevin Chiu0b1a90d2016-10-03 17:15:15 +0800119
120 # Minimum SLP S3 assertion width 28ms.
121 register "slp_s3_assertion_width_usecs" = "28000"
122
123 device domain 0 on
124 device pci 00.0 on end # - Host Bridge
125 device pci 00.1 on end # - DPTF
126 device pci 00.2 on end # - NPK
127 device pci 02.0 on end # - Gen
128 device pci 03.0 on end # - Iunit
129 device pci 0d.0 on end # - P2SB
130 device pci 0d.1 on end # - PMC
131 device pci 0d.2 on end # - SPI
132 device pci 0d.3 on end # - Shared SRAM
133 device pci 0e.0 on # - Audio
134 chip drivers/generic/max98357a
Martin Roth2e6aeba2016-10-07 10:48:31 -0600135 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"
Kevin Chiu49ef5aa2016-11-09 14:23:06 +0800136 register "sdmode_delay" = "5"
Kevin Chiu0b1a90d2016-10-03 17:15:15 +0800137 device generic 0 on end
138 end
139 end
140 device pci 11.0 off end # - ISH
141 device pci 12.0 off end # - SATA
142 device pci 13.0 off end # - Root Port 2 - PCIe-A 0
143 device pci 13.1 off end # - Root Port 3 - PCIe-A 1
144 device pci 13.2 off end # - Root Port 4 - PCIe-A 2
145 device pci 13.3 off end # - Root Port 5 - PCIe-A 3
146 device pci 14.0 on
147 chip drivers/intel/wifi
148 register "wake" = "GPE0_DW3_00"
149 device pci 00.0 on end
150 end
151 end # - Root Port 0 - PCIe-B 0 - Wifi
152 device pci 14.1 off end # - Root Port 1 - PCIe-B 1
153 device pci 15.0 on end # - XHCI
154 device pci 15.1 off end # - XDCI
155 device pci 16.0 on # - I2C 0
156 chip drivers/i2c/da7219
157 register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)"
158 register "btn_cfg" = "50"
159 register "mic_det_thr" = "500"
160 register "jack_ins_deb" = "20"
161 register "jack_det_rate" = ""32ms_64ms""
162 register "jack_rem_deb" = "1"
163 register "a_d_btn_thr" = "0xa"
164 register "d_b_btn_thr" = "0x16"
165 register "b_c_btn_thr" = "0x21"
166 register "c_mic_btn_thr" = "0x3e"
167 register "btn_avg" = "4"
168 register "adc_1bit_rpt" = "1"
169 register "micbias_lvl" = "2600"
170 register "mic_amp_in_sel" = ""diff""
171 device i2c 1a on end
172 end
173 end
174 device pci 16.1 on end # - I2C 1
175 device pci 16.2 on
176 chip drivers/i2c/tpm
177 register "hid" = ""GOOG0005""
178 register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)"
179 device i2c 50 on end
180 end
181 end # - I2C 2
182 device pci 16.3 on
Furquan Shaikh8be4fdf2016-10-21 16:45:59 -0700183 chip drivers/i2c/wacom_ts
184 register "generic" = "{
Janice Lie19c80b2016-11-07 17:49:44 +0800185 .hid = WCOMNTN2_HID,
Furquan Shaikh8be4fdf2016-10-21 16:45:59 -0700186 .cid = PNP0C50_CID,
187 .desc = WCOM_TS_DESC,
188 .irq = IRQ_EDGE_LOW(GPIO_21_IRQ),
189 .probed = 1,
190 }"
191 register "hid_desc_reg_offset" = "0x1"
192 device i2c 0xA on end
Kevin Chiu0b1a90d2016-10-03 17:15:15 +0800193 end
194 end # - I2C 3
195 device pci 17.0 on
196 chip drivers/i2c/generic
197 register "hid" = ""ELAN0000""
198 register "desc" = ""ELAN Touchpad""
199 register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)"
200 register "wake" = "GPE0_DW1_15"
201 register "probed" = "1"
202 device i2c 15 on end
203 end
204 end # - I2C 4
205 device pci 17.1 on end # - I2C 5
206 device pci 17.2 on end # - I2C 6
207 device pci 17.3 on end # - I2C 7
208 device pci 18.0 on end # - UART 0
209 device pci 18.1 on end # - UART 1
210 device pci 18.2 on end # - UART 2
211 device pci 18.3 on end # - UART 3
212 device pci 19.0 on end # - SPI 0
213 device pci 19.1 on end # - SPI 1
214 device pci 19.2 on end # - SPI 2
215 device pci 1a.0 on end # - PWM
216 device pci 1b.0 on end # - SDCARD
217 device pci 1c.0 on end # - eMMC
218 device pci 1e.0 off end # - SDIO
219 device pci 1f.0 on # - LPC
220 chip ec/google/chromeec
221 device pnp 0c09.0 on end
222 end
223 end
224 device pci 1f.1 on end # - SMBUS
225 end
226end