Elyes HAOUAS | f7b2fe6 | 2020-05-07 12:38:15 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
Lee Leahy | 2ed7eb7 | 2016-01-01 18:08:48 -0800 | [diff] [blame] | 2 | |
| 3 | config SOC_INTEL_QUARK |
| 4 | bool |
| 5 | help |
| 6 | Intel Quark support |
| 7 | |
| 8 | if SOC_INTEL_QUARK |
| 9 | |
| 10 | config CPU_SPECIFIC_OPTIONS |
| 11 | def_bool y |
Kyösti Mälkki | 10bdee1 | 2023-04-11 01:00:17 +0300 | [diff] [blame] | 12 | select ACPI_NO_CUSTOM_MADT |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 13 | select ARCH_X86 |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 14 | select NO_ECAM_MMCONF_SUPPORT |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 15 | select NO_SMM |
Lee Leahy | 4dd34ee | 2016-05-02 14:31:02 -0700 | [diff] [blame] | 16 | select REG_SCRIPT |
Michael Niewöhner | b17f3d3 | 2019-10-24 00:19:45 +0200 | [diff] [blame] | 17 | select PLATFORM_USES_FSP2_0 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 18 | select SOC_INTEL_COMMON |
Lee Leahy | 6e8233a | 2016-07-30 10:34:22 -0700 | [diff] [blame] | 19 | select SOC_INTEL_COMMON_RESET |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 20 | select SOC_SETS_MSRS |
Lee Leahy | d935109 | 2017-05-24 13:23:26 -0700 | [diff] [blame] | 21 | select SPI_FLASH |
Lee Leahy | 6ec72c9 | 2016-05-07 09:04:46 -0700 | [diff] [blame] | 22 | select UART_OVERRIDE_REFCLK |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 23 | select UDELAY_TSC |
Kyösti Mälkki | ddd6ca7 | 2019-11-01 18:25:46 +0200 | [diff] [blame] | 24 | select TSC_MONOTONIC_TIMER |
Lee Leahy | 43cdff6 | 2016-02-07 14:52:22 -0800 | [diff] [blame] | 25 | select UNCOMPRESSED_RAMSTAGE |
Subrata Banik | 34f26b2 | 2022-02-10 12:38:02 +0530 | [diff] [blame] | 26 | select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM |
| 27 | select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT |
| 28 | select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE |
Lee Leahy | 2ed7eb7 | 2016-01-01 18:08:48 -0800 | [diff] [blame] | 29 | select USE_MARCH_586 |
| 30 | |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 31 | ##### |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 32 | # Debug serial output |
| 33 | # The following options configure the debug serial port |
| 34 | ##### |
| 35 | |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 36 | config ENABLE_BUILTIN_HSUART0 |
| 37 | bool "Enable built-in HSUART0" |
| 38 | default n |
| 39 | select NO_UART_ON_SUPERIO |
| 40 | select DRIVERS_UART_8250MEM_32 |
| 41 | help |
| 42 | The Quark SoC has two HSUART. Choose this option to configure the pads |
| 43 | and enable HSUART0, which can be used for the debug console. |
| 44 | |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 45 | config ENABLE_BUILTIN_HSUART1 |
| 46 | bool "Enable built-in HSUART1" |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 47 | default n |
| 48 | depends on ! ENABLE_BUILTIN_HSUART0 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 49 | select NO_UART_ON_SUPERIO |
| 50 | select DRIVERS_UART_8250MEM_32 |
| 51 | help |
| 52 | The Quark SoC has two HSUART. Choose this option to configure the pads |
| 53 | and enable HSUART1, which can be used for the debug console. |
| 54 | |
| 55 | config TTYS0_BASE |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 56 | hex "HSUART Base Address" |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 57 | default 0xA0019000 |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 58 | depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 59 | help |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 60 | Memory mapped MMIO of HSUART. |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 61 | |
| 62 | config TTYS0_LCS |
| 63 | int |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 64 | default 3 |
Lee Leahy | bc518d5 | 2016-05-30 15:01:06 -0700 | [diff] [blame] | 65 | depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 66 | |
| 67 | ##### |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 68 | # Debug support |
| 69 | # The following options provide debug support for the Quark coreboot |
| 70 | # code. The SD LED is used as a binary marker to determine if a |
| 71 | # specific point in the execution flow has been reached. |
| 72 | ##### |
| 73 | |
| 74 | config ENABLE_DEBUG_LED |
| 75 | bool |
| 76 | default n |
| 77 | help |
| 78 | Enable the use of the SD LED for early debugging before serial output |
| 79 | is available. Setting this LED indicates that control has reached the |
| 80 | desired check point. |
| 81 | |
| 82 | config ENABLE_DEBUG_LED_ESRAM |
| 83 | bool "SD LED indicates ESRAM initialized" |
| 84 | default n |
| 85 | select ENABLE_DEBUG_LED |
| 86 | help |
Lee Leahy | a765090 | 2016-12-28 11:43:10 -0800 | [diff] [blame] | 87 | Indicate that ESRAM has been successfully initialized. If the SD LED |
| 88 | does not light then the ESRAM initialization needs to be debugged. |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 89 | |
Lee Leahy | a765090 | 2016-12-28 11:43:10 -0800 | [diff] [blame] | 90 | config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY |
| 91 | bool "SD LED indicates bootblock.c successfully entered" |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 92 | default n |
| 93 | select ENABLE_DEBUG_LED |
| 94 | help |
Lee Leahy | a765090 | 2016-12-28 11:43:10 -0800 | [diff] [blame] | 95 | Indicate that bootblock_c_entry was entered. If the SD LED does not |
Michael Niewöhner | b17f3d3 | 2019-10-24 00:19:45 +0200 | [diff] [blame] | 96 | light then debug the code between ESRAM and bootblock_c_entry. |
Lee Leahy | a765090 | 2016-12-28 11:43:10 -0800 | [diff] [blame] | 97 | |
| 98 | config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY |
| 99 | bool "SD LED indicates bootblock_soc_early_init successfully entered" |
| 100 | default n |
| 101 | select ENABLE_DEBUG_LED |
| 102 | help |
| 103 | Indicate that bootblock_soc_early_init was entered. If the SD LED |
| 104 | does not light then debug the code in bootblock_main_with_timestamp. |
| 105 | |
| 106 | config ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT |
| 107 | bool "SD LED indicates bootblock_soc_early_init successfully exited" |
| 108 | default n |
| 109 | select ENABLE_DEBUG_LED |
| 110 | help |
| 111 | Indicate that bootblock_soc_early_init exited. If the SD LED does not |
| 112 | light then debug the scripts in bootblock_soc_early_init. |
| 113 | |
| 114 | config ENABLE_DEBUG_LED_SOC_INIT_ENTRY |
| 115 | bool "SD LED indicates bootblock_soc_init successfully entered" |
| 116 | default n |
| 117 | select ENABLE_DEBUG_LED |
| 118 | help |
| 119 | Indicate that bootblock_soc_init was entered. If the SD LED does not |
| 120 | light then debug the code in bootblock_mainboard_early_init and |
| 121 | console_init. If the SD LED does light but there is no serial then |
| 122 | debug the serial port configuration and initialization. |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 123 | |
| 124 | ##### |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 125 | # ESRAM layout |
| 126 | # Specify the portion of the ESRAM for coreboot to use as its data area. |
| 127 | ##### |
| 128 | |
| 129 | config DCACHE_RAM_BASE |
| 130 | hex |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 131 | default 0x80000000 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 132 | |
| 133 | config DCACHE_RAM_SIZE |
| 134 | hex |
Lee Leahy | 102f625 | 2016-07-25 07:41:54 -0700 | [diff] [blame] | 135 | default 0x40000 |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 136 | |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 137 | config DISPLAY_ESRAM_LAYOUT |
| 138 | bool "Display ESRAM layout" |
| 139 | default n |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 140 | help |
| 141 | Select this option to display coreboot's use of ESRAM. |
| 142 | |
Lee Leahy | 87df8d0 | 2016-02-07 14:37:13 -0800 | [diff] [blame] | 143 | ##### |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 144 | # Flash layout |
| 145 | # Specify the size of the coreboot file system in the read-only |
| 146 | # (recovery) portion of the flash part. |
| 147 | ##### |
| 148 | |
| 149 | config CBFS_SIZE |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 150 | default 0x200000 |
| 151 | help |
| 152 | Specify the size of the coreboot file system in the read-only (recovery) |
| 153 | portion of the flash part. On Quark systems the firmware image stores |
| 154 | more than just coreboot, including: |
| 155 | - The chipset microcode (RMU) binary file located at 0xFFF00000 |
| 156 | - Intel Trusted Execution Engine firmware |
| 157 | |
| 158 | ##### |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 159 | # FSP binary |
| 160 | # The following options control the FSP binary file placement in |
| 161 | # the flash image and ESRAM. This file is required by the Quark |
| 162 | # SoC code to boot coreboot and its payload. |
| 163 | ##### |
| 164 | |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 165 | config FSP_ESRAM_LOC |
| 166 | hex |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 167 | default 0x80040000 |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 168 | help |
| 169 | The location in ESRAM where a copy of the FSP binary is placed. |
| 170 | |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 171 | config FSP_M_FILE |
| 172 | string |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 173 | default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd" |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 174 | |
| 175 | config FSP_S_FILE |
| 176 | string |
Patrick Georgi | b8fba86 | 2020-06-17 21:06:53 +0200 | [diff] [blame] | 177 | default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd" |
Lee Leahy | f26fc0f | 2016-07-25 10:14:07 -0700 | [diff] [blame] | 178 | |
Lee Leahy | a7ba56e | 2016-02-07 10:42:14 -0800 | [diff] [blame] | 179 | ##### |
Lee Leahy | 9fd0895 | 2016-02-02 07:17:06 -0800 | [diff] [blame] | 180 | # RMU binary |
| 181 | # The following options control the Quark chipset microcode file |
| 182 | # placement in the flash image. This file is required to bring |
| 183 | # the Quark processor out of reset. |
| 184 | ##### |
| 185 | |
| 186 | config ADD_RMU_FILE |
| 187 | bool "Should the RMU binary be added to the flash image?" |
| 188 | default n |
| 189 | help |
| 190 | The RMU file is required to get the chip out of reset. |
| 191 | |
| 192 | config RMU_FILE |
| 193 | string |
| 194 | default "3rdparty/blobs/soc/intel/quark/rmu.bin" |
| 195 | depends on ADD_RMU_FILE |
| 196 | help |
| 197 | The path and filename of the Intel Quark RMU binary. |
| 198 | |
| 199 | config RMU_LOC |
| 200 | hex |
| 201 | default 0xfff00000 |
| 202 | depends on ADD_RMU_FILE |
| 203 | help |
| 204 | The location in CBFS that the RMU is located. It must match the |
| 205 | strap-determined base address. |
| 206 | |
Lee Leahy | ce9e21a | 2016-06-05 18:48:31 -0700 | [diff] [blame] | 207 | config DCACHE_BSP_STACK_SIZE |
| 208 | hex |
| 209 | default 0x4000 |
| 210 | |
Lee Leahy | 16bc9ba | 2017-04-01 20:33:58 -0700 | [diff] [blame] | 211 | ##### |
| 212 | # Test support |
| 213 | ##### |
| 214 | |
| 215 | config STORAGE_TEST |
| 216 | bool "Test SD/MMC/eMMC card or device access" |
| 217 | default n |
Lee Leahy | 48dbc66 | 2017-05-08 16:56:03 -0700 | [diff] [blame] | 218 | select COMMONLIB_STORAGE |
Lee Leahy | 16bc9ba | 2017-04-01 20:33:58 -0700 | [diff] [blame] | 219 | select SDHCI_CONTROLLER |
| 220 | help |
Martin Roth | 26f97f9 | 2021-10-01 14:53:22 -0600 | [diff] [blame] | 221 | Read block 0 from each partition of the storage device. User |
Lee Leahy | 48dbc66 | 2017-05-08 16:56:03 -0700 | [diff] [blame] | 222 | must also enable one or both of COMMONLIB_STORAGE_SD or |
| 223 | COMMONLIB_STORAGE_MMC. |
Lee Leahy | 16bc9ba | 2017-04-01 20:33:58 -0700 | [diff] [blame] | 224 | |
| 225 | config STORAGE_LOG |
| 226 | bool "Log and display SD/MMC commands" |
| 227 | default n |
| 228 | depends on STORAGE_TEST |
| 229 | |
Lee Leahy | 5764cbb | 2017-06-29 17:29:07 -0700 | [diff] [blame] | 230 | ##### |
| 231 | # I2C debug support |
| 232 | ##### |
| 233 | |
| 234 | config I2C_DEBUG |
| 235 | bool "Enable I2C debugging" |
| 236 | default n |
| 237 | help |
| 238 | Display the I2C segments and controller errors |
| 239 | |
Lee Leahy | 2ed7eb7 | 2016-01-01 18:08:48 -0800 | [diff] [blame] | 240 | endif # SOC_INTEL_QUARK |