Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2006 AMD |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 5 | * (Written by Yinghai Lu <yinghailu@amd.com> for AMD) |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 6 | * Copyright (C) 2006 MSI |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 7 | * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI) |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 8 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 23 | */ |
| 24 | |
| 25 | #define ASSEMBLY 1 |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 26 | #define __PRE_RAM__ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 27 | |
| 28 | #define RAMINIT_SYSINFO 1 |
| 29 | |
| 30 | #define CACHE_AS_RAM_ADDRESS_DEBUG 0 |
| 31 | |
| 32 | unsigned int get_sbdn(unsigned bus); |
| 33 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 34 | /* Used by raminit. */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 35 | #define QRANK_DIMM_SUPPORT 1 |
| 36 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 37 | /* Used by init_cpus and fidvid */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 38 | #define K8_SET_FIDVID 1 |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 39 | |
| 40 | /* If we want to wait for core1 done before DQS training, set it to 0. */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 41 | #define K8_SET_FIDVID_CORE0_ONLY 1 |
| 42 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 43 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 44 | #include <string.h> |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 45 | #include <device/pci_def.h> |
| 46 | #include <arch/io.h> |
| 47 | #include <device/pnp_def.h> |
| 48 | #include <arch/romcc_io.h> |
| 49 | #include <cpu/x86/lapic.h> |
| 50 | #include "option_table.h" |
| 51 | #include "pc80/mc146818rtc_early.c" |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 52 | #include "pc80/serial.c" |
| 53 | #include "arch/i386/lib/console.c" |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 54 | #include <cpu/amd/model_fxx_rev.h> |
| 55 | #include "northbridge/amd/amdk8/raminit.h" |
| 56 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 57 | #include "lib/delay.c" |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 58 | #include "cpu/x86/lapic/boot_cpu.c" |
| 59 | #include "northbridge/amd/amdk8/reset_test.c" |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 60 | #include "northbridge/amd/amdk8/early_ht.c" |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 61 | #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" |
| 62 | #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame^] | 63 | #include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 64 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 65 | #include "cpu/x86/bist.h" |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 66 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 67 | |
| 68 | #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) |
| 69 | #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) |
Rudolf Marek | 6211ae1 | 2008-01-12 22:29:17 +0000 | [diff] [blame] | 70 | #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 71 | #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC) |
| 72 | |
| 73 | static void memreset_setup(void) |
| 74 | { |
| 75 | } |
| 76 | |
| 77 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 78 | { |
| 79 | } |
| 80 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 81 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 82 | { |
| 83 | return smbus_read_byte(device, address); |
| 84 | } |
| 85 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 86 | void activate_spd_rom(const struct mem_controller *ctrl) |
| 87 | { |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 88 | } |
| 89 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 90 | void soft_reset(void) |
| 91 | { |
| 92 | uint8_t tmp; |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 93 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 94 | set_bios_reset(); |
| 95 | print_debug("soft reset \r\n"); |
| 96 | |
| 97 | /* PCI reset */ |
| 98 | tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); |
| 99 | tmp |= 0x01; |
| 100 | pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); |
| 101 | |
| 102 | while (1) { |
| 103 | /* daisy daisy ... */ |
| 104 | hlt(); |
| 105 | } |
| 106 | } |
| 107 | |
Carl-Daniel Hailfinger | 3f04dad | 2009-04-13 16:21:16 +0000 | [diff] [blame] | 108 | #define K8_4RANK_DIMM_SUPPORT 1 |
| 109 | |
| 110 | #include "northbridge/amd/amdk8/amdk8.h" |
| 111 | #include "northbridge/amd/amdk8/raminit.c" |
| 112 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 113 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 114 | #include "lib/generic_sdram.c" |
Carl-Daniel Hailfinger | 3f04dad | 2009-04-13 16:21:16 +0000 | [diff] [blame] | 115 | #include "cpu/amd/dualcore/dualcore.c" |
| 116 | #include "southbridge/via/k8t890/k8t890_early_car.c" |
| 117 | #include "cpu/amd/car/copy_and_run.c" |
| 118 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 119 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 120 | #include "cpu/amd/model_fxx/fidvid.c" |
| 121 | #include "northbridge/amd/amdk8/resourcemap.c" |
| 122 | |
| 123 | void hard_reset(void) |
| 124 | { |
| 125 | print_info("NO HARD RESET. FIX ME!\n"); |
| 126 | } |
| 127 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 128 | unsigned int get_sbdn(unsigned bus) |
| 129 | { |
| 130 | device_t dev; |
| 131 | |
| 132 | dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, |
| 133 | PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); |
| 134 | return (dev >> 15) & 0x1f; |
| 135 | } |
| 136 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 137 | void sio_init(void) |
| 138 | { |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 139 | u8 reg; |
| 140 | |
| 141 | pnp_enter_ext_func_mode(SERIAL_DEV); |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 142 | /* We have 24MHz input. */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 143 | reg = pnp_read_config(SERIAL_DEV, 0x24); |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 144 | pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); |
| 145 | /* We have GPIO for KB/MS pin. */ |
| 146 | reg = pnp_read_config(SERIAL_DEV, 0x2a); |
| 147 | pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1)); |
| 148 | /* We have all RESTOUT and even some reserved bits, too. */ |
| 149 | reg = pnp_read_config(SERIAL_DEV, 0x2c); |
| 150 | pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0)); |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 151 | pnp_exit_ext_func_mode(SERIAL_DEV); |
| 152 | |
Rudolf Marek | 6211ae1 | 2008-01-12 22:29:17 +0000 | [diff] [blame] | 153 | pnp_enter_ext_func_mode(ACPI_DEV); |
| 154 | pnp_set_logical_device(ACPI_DEV); |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 155 | /* |
| 156 | * Set the delay rising time from PWROK_LP to PWROK_ST to |
| 157 | * 300 - 600ms, and 0 to vice versa. |
| 158 | */ |
Rudolf Marek | 6211ae1 | 2008-01-12 22:29:17 +0000 | [diff] [blame] | 159 | reg = pnp_read_config(ACPI_DEV, 0xe6); |
Rudolf Marek | 6211ae1 | 2008-01-12 22:29:17 +0000 | [diff] [blame] | 160 | pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0)); |
| 161 | /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */ |
| 162 | reg = pnp_read_config(ACPI_DEV, 0xe4); |
| 163 | pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10)); |
| 164 | pnp_exit_ext_func_mode(ACPI_DEV); |
| 165 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 166 | pnp_enter_ext_func_mode(GPIO_DEV); |
| 167 | pnp_set_logical_device(GPIO_DEV); |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 168 | /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */ |
| 169 | pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */ |
| 170 | pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */ |
| 171 | pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */ |
| 172 | pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */ |
| 173 | pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */ |
| 174 | pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */ |
| 175 | pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */ |
Rudolf Marek | 6211ae1 | 2008-01-12 22:29:17 +0000 | [diff] [blame] | 176 | pnp_exit_ext_func_mode(GPIO_DEV); |
| 177 | } |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 178 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 179 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
Rudolf Marek | 6211ae1 | 2008-01-12 22:29:17 +0000 | [diff] [blame] | 180 | |
| 181 | void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) |
| 182 | { |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 183 | /* unsigned last_boot_normal_x = last_boot_normal(); */ |
| 184 | /* FIXME */ |
Rudolf Marek | 6211ae1 | 2008-01-12 22:29:17 +0000 | [diff] [blame] | 185 | unsigned last_boot_normal_x = 1; |
| 186 | |
| 187 | sio_init(); |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 188 | w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 189 | uart_init(); |
| 190 | console_init(); |
Rudolf Marek | 5671787 | 2008-03-15 00:26:50 +0000 | [diff] [blame] | 191 | enable_rom_decode(); |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 192 | |
| 193 | print_info("now booting... fallback\r\n"); |
| 194 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 195 | /* Is this a CPU only reset? Or is this a secondary CPU? */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 196 | if ((cpu_init_detectedx) || (!boot_cpu())) { |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 197 | if (last_boot_normal_x) |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 198 | goto normal_image; |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 199 | else |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 200 | goto fallback_image; |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 201 | } |
| 202 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 203 | /* Nothing special needs to be done to find bus 0. */ |
| 204 | /* Allow the HT devices to be found. */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 205 | enumerate_ht_chain(); |
| 206 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 207 | /* Is this a deliberate reset by the BIOS? */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 208 | if (bios_reset_detected() && last_boot_normal_x) { |
| 209 | goto normal_image; |
| 210 | } |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 211 | /* This is the primary CPU, how should I boot? */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 212 | else if (do_normal_boot()) { |
| 213 | goto normal_image; |
| 214 | } else { |
| 215 | goto fallback_image; |
| 216 | } |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 217 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 218 | normal_image: |
| 219 | /* print_info("JMP normal image\r\n"); */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 220 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 221 | __asm__ __volatile__("jmp __normal_image": |
| 222 | :"a" (bist), "b" (cpu_init_detectedx)); |
| 223 | |
| 224 | fallback_image: |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 225 | ; |
| 226 | } |
| 227 | #endif |
| 228 | |
| 229 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx); |
| 230 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 231 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 232 | { |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 233 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 234 | failover_process(bist, cpu_init_detectedx); |
| 235 | #endif |
| 236 | real_main(bist, cpu_init_detectedx); |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 237 | } |
| 238 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 239 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 240 | { |
| 241 | static const uint16_t spd_addr[] = { |
| 242 | (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, |
| 243 | (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, |
| 244 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 245 | (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, |
| 246 | (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, |
| 247 | #endif |
| 248 | }; |
| 249 | unsigned bsp_apicid = 0; |
| 250 | int needs_reset = 0; |
| 251 | struct sys_info *sysinfo = |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 252 | (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 253 | char *p; |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 254 | |
Rudolf Marek | 6211ae1 | 2008-01-12 22:29:17 +0000 | [diff] [blame] | 255 | sio_init(); |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 256 | w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 257 | uart_init(); |
| 258 | console_init(); |
Rudolf Marek | 5671787 | 2008-03-15 00:26:50 +0000 | [diff] [blame] | 259 | enable_rom_decode(); |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 260 | |
| 261 | print_info("now booting... real_main\r\n"); |
| 262 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 263 | if (bist == 0) |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 264 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 265 | |
| 266 | /* Halt if there was a built in self test failure. */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 267 | report_bist_failure(bist); |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 268 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 269 | setup_default_resource_map(); |
| 270 | setup_coherent_ht_domain(); |
| 271 | wait_all_core0_started(); |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 272 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 273 | print_info("now booting... Core0 started\r\n"); |
| 274 | |
| 275 | #if CONFIG_LOGICAL_CPUS==1 |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 276 | /* It is said that we should start core1 after all core0 launched. */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 277 | start_other_cores(); |
| 278 | wait_all_other_cores_started(bsp_apicid); |
| 279 | #endif |
| 280 | init_timer(); |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 281 | ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ |
Rudolf Marek | cc3ccdb | 2007-11-13 15:40:21 +0000 | [diff] [blame] | 282 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 283 | needs_reset = optimize_link_coherent_ht(); |
| 284 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
Rudolf Marek | c221349 | 2008-03-19 20:24:33 +0000 | [diff] [blame] | 285 | needs_reset |= k8t890_early_setup_ht(); |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 286 | |
| 287 | if (needs_reset) { |
| 288 | print_debug("ht reset -\r\n"); |
| 289 | soft_reset(); |
| 290 | } |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 291 | |
Rudolf Marek | c221349 | 2008-03-19 20:24:33 +0000 | [diff] [blame] | 292 | /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ |
| 293 | enable_fid_change(); |
| 294 | init_fidvid_bsp(bsp_apicid); |
| 295 | |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 296 | /* Stop the APs so we can start them later in init. */ |
| 297 | allow_all_aps_stop(bsp_apicid); |
| 298 | |
| 299 | /* It's the time to set ctrl now. */ |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 300 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
Uwe Hermann | c4f5365 | 2008-03-08 19:14:42 +0000 | [diff] [blame] | 301 | |
Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame] | 302 | enable_smbus(); |
| 303 | memreset_setup(); |
| 304 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 305 | post_cache_as_ram(); |
| 306 | } |