Rudolf Marek | 1a00256 | 2007-11-02 23:17:57 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the LinuxBIOS project. |
| 3 | * |
| 4 | * Copyright (C) 2006 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * Copyright (C) 2006 MSI |
| 7 | * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI. |
| 8 | * |
| 9 | * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 24 | */ |
| 25 | |
| 26 | #define ASSEMBLY 1 |
| 27 | #define __ROMCC__ |
| 28 | |
| 29 | #define RAMINIT_SYSINFO 1 |
| 30 | |
| 31 | #define CACHE_AS_RAM_ADDRESS_DEBUG 0 |
| 32 | |
| 33 | unsigned int get_sbdn(unsigned bus); |
| 34 | |
| 35 | //used by raminit |
| 36 | #define QRANK_DIMM_SUPPORT 1 |
| 37 | |
| 38 | //used by init_cpus and fidvid |
| 39 | #define K8_SET_FIDVID 1 |
| 40 | //if we want to wait for core1 done before DQS training, set it to 0 |
| 41 | #define K8_SET_FIDVID_CORE0_ONLY 1 |
| 42 | |
| 43 | //#define DEBUG_SMBUS 1 |
| 44 | |
| 45 | #include <stdint.h> |
| 46 | #include <device/pci_def.h> |
| 47 | #include <arch/io.h> |
| 48 | #include <device/pnp_def.h> |
| 49 | #include <arch/romcc_io.h> |
| 50 | #include <cpu/x86/lapic.h> |
| 51 | #include "option_table.h" |
| 52 | #include "pc80/mc146818rtc_early.c" |
| 53 | |
| 54 | #include "pc80/serial.c" |
| 55 | #include "arch/i386/lib/console.c" |
| 56 | |
| 57 | #include <cpu/amd/model_fxx_rev.h> |
| 58 | #include "northbridge/amd/amdk8/raminit.h" |
| 59 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 60 | #include "lib/delay.c" |
| 61 | |
| 62 | #if CONFIG_USE_INIT == 0 |
| 63 | #include "lib/memcpy.c" |
| 64 | #endif |
| 65 | |
| 66 | #include "cpu/x86/lapic/boot_cpu.c" |
| 67 | #include "northbridge/amd/amdk8/reset_test.c" |
| 68 | #include "northbridge/amd/amdk8/debug.c" |
| 69 | #include "northbridge/amd/amdk8/early_ht.c" |
| 70 | |
| 71 | |
| 72 | #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" |
| 73 | #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" |
| 74 | |
| 75 | #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| 76 | #include "cpu/x86/bist.h" |
| 77 | |
| 78 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 79 | |
| 80 | #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) |
| 81 | #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) |
| 82 | #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC) |
| 83 | |
| 84 | static void memreset_setup(void) |
| 85 | { |
| 86 | } |
| 87 | |
| 88 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 89 | { |
| 90 | } |
| 91 | |
| 92 | |
| 93 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 94 | { |
| 95 | return smbus_read_byte(device, address); |
| 96 | } |
| 97 | |
| 98 | #define K8_4RANK_DIMM_SUPPORT 1 |
| 99 | |
| 100 | #include "northbridge/amd/amdk8/amdk8.h" |
| 101 | #include "northbridge/amd/amdk8/raminit.c" |
| 102 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 103 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 104 | #include "sdram/generic_sdram.c" |
| 105 | |
| 106 | #include "cpu/amd/dualcore/dualcore.c" |
| 107 | |
| 108 | #include "southbridge/via/k8t890/k8t890_early_car.c" |
| 109 | |
| 110 | #include "cpu/amd/car/copy_and_run.c" |
| 111 | |
| 112 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 113 | |
| 114 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 115 | #include "cpu/amd/model_fxx/fidvid.c" |
| 116 | |
| 117 | #include "northbridge/amd/amdk8/resourcemap.c" |
| 118 | |
| 119 | |
| 120 | void activate_spd_rom(const struct mem_controller *ctrl) |
| 121 | { |
| 122 | |
| 123 | } |
| 124 | |
| 125 | void hard_reset(void) |
| 126 | { |
| 127 | print_info("NO HARD RESET FIX ME!\n"); |
| 128 | } |
| 129 | |
| 130 | void soft_reset(void) |
| 131 | { |
| 132 | uint8_t tmp; |
| 133 | set_bios_reset(); |
| 134 | print_debug("soft reset \r\n"); |
| 135 | |
| 136 | /* PCI reset */ |
| 137 | tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); |
| 138 | tmp |= 0x01; |
| 139 | pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); |
| 140 | |
| 141 | while (1) { |
| 142 | /* daisy daisy ... */ |
| 143 | hlt(); |
| 144 | } |
| 145 | } |
| 146 | |
| 147 | unsigned int get_sbdn(unsigned bus) |
| 148 | { |
| 149 | device_t dev; |
| 150 | |
| 151 | dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, |
| 152 | PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); |
| 153 | return (dev >> 15) & 0x1f; |
| 154 | } |
| 155 | |
| 156 | #if USE_FALLBACK_IMAGE == 1 |
| 157 | |
| 158 | void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) |
| 159 | { |
| 160 | // unsigned last_boot_normal_x = last_boot_normal(); |
| 161 | //FIXME |
| 162 | unsigned last_boot_normal_x = 1; |
| 163 | u8 reg; |
| 164 | |
| 165 | pnp_enter_ext_func_mode(SERIAL_DEV); |
| 166 | reg = pnp_read_config(SERIAL_DEV, 0x24); |
| 167 | pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* we have 24MHz input */ |
| 168 | |
| 169 | reg = pnp_read_config(SERIAL_DEV, 0x2A); |
| 170 | pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1)); /* we have GPIO for KB/MS PIN */ |
| 171 | |
| 172 | reg = pnp_read_config(SERIAL_DEV, 0x2C); |
| 173 | pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0)); /* we have all RESTOUT and even some reserved bits too */ |
| 174 | |
| 175 | pnp_exit_ext_func_mode(SERIAL_DEV); |
| 176 | |
| 177 | pnp_enter_ext_func_mode(GPIO_DEV); |
| 178 | pnp_set_logical_device(GPIO_DEV); |
| 179 | pnp_write_config(GPIO_DEV, 0xe0, 0xde); // 1101110 0=output 1=input |
| 180 | pnp_write_config(GPIO_DEV, 0xe1, 0x1); //set output val |
| 181 | pnp_write_config(GPIO_DEV, 0xe2, 0x0); //no inversion |
| 182 | pnp_write_config(GPIO_DEV, 0xe3, 0x3); //0000 0011 0=output 1=input |
| 183 | pnp_write_config(GPIO_DEV, 0xe4, 0xa4); //set output val |
| 184 | pnp_write_config(GPIO_DEV, 0xe5, 0x0); //no inversion |
| 185 | pnp_write_config(GPIO_DEV, 0x30, 0x9); //Enable GPIO 2 & GPIO 5 |
| 186 | pnp_exit_ext_func_mode(GPIO_DEV); |
| 187 | |
| 188 | |
| 189 | w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); |
| 190 | uart_init(); |
| 191 | console_init(); |
| 192 | |
| 193 | print_info("now booting... fallback\r\n"); |
| 194 | |
| 195 | /* Is this a cpu only reset? or Is this a secondary cpu? */ |
| 196 | if ((cpu_init_detectedx) || (!boot_cpu())) { |
| 197 | if (last_boot_normal_x) { |
| 198 | goto normal_image; |
| 199 | } else { |
| 200 | goto fallback_image; |
| 201 | } |
| 202 | } |
| 203 | |
| 204 | /* Nothing special needs to be done to find bus 0 */ |
| 205 | /* Allow the HT devices to be found */ |
| 206 | |
| 207 | enumerate_ht_chain(); |
| 208 | |
| 209 | /* Is this a deliberate reset by the bios */ |
| 210 | if (bios_reset_detected() && last_boot_normal_x) { |
| 211 | goto normal_image; |
| 212 | } |
| 213 | /* This is the primary cpu how should I boot? */ |
| 214 | else if (do_normal_boot()) { |
| 215 | goto normal_image; |
| 216 | } else { |
| 217 | goto fallback_image; |
| 218 | } |
| 219 | normal_image: |
| 220 | //print_info("JMP normal image\r\n"); |
| 221 | |
| 222 | __asm__ volatile ("jmp __normal_image": /* outputs */ |
| 223 | :"a" (bist), "b"(cpu_init_detectedx) /* inputs */ |
| 224 | ); |
| 225 | |
| 226 | fallback_image: |
| 227 | ; |
| 228 | } |
| 229 | #endif |
| 230 | |
| 231 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx); |
| 232 | |
| 233 | void cache_as_ram_main(unsigned long bist, |
| 234 | unsigned long cpu_init_detectedx) |
| 235 | { |
| 236 | |
| 237 | #if USE_FALLBACK_IMAGE == 1 |
| 238 | failover_process(bist, cpu_init_detectedx); |
| 239 | #endif |
| 240 | real_main(bist, cpu_init_detectedx); |
| 241 | |
| 242 | } |
| 243 | |
| 244 | |
| 245 | void real_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 246 | { |
| 247 | static const uint16_t spd_addr[] = { |
| 248 | (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, |
| 249 | (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, |
| 250 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 251 | (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, |
| 252 | (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, |
| 253 | #endif |
| 254 | }; |
| 255 | unsigned bsp_apicid = 0; |
| 256 | int needs_reset = 0; |
| 257 | struct sys_info *sysinfo = |
| 258 | (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - |
| 259 | DCACHE_RAM_GLOBAL_VAR_SIZE); |
| 260 | char *p; |
| 261 | u8 reg; |
| 262 | |
| 263 | pnp_enter_ext_func_mode(SERIAL_DEV); |
| 264 | reg = pnp_read_config(SERIAL_DEV, 0x24); |
| 265 | pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40)); /* we have 24MHz input */ |
| 266 | |
| 267 | reg = pnp_read_config(SERIAL_DEV, 0x2A); |
| 268 | pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1)); /* we have GPIO for KB/MS PIN */ |
| 269 | |
| 270 | reg = pnp_read_config(SERIAL_DEV, 0x2C); |
| 271 | pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0)); /* we have all RESTOUT and even some reserved bits too */ |
| 272 | |
| 273 | pnp_exit_ext_func_mode(SERIAL_DEV); |
| 274 | |
| 275 | pnp_enter_ext_func_mode(GPIO_DEV); |
| 276 | pnp_set_logical_device(GPIO_DEV); |
| 277 | pnp_write_config(GPIO_DEV, 0xe0, 0xde); // 1101110 0=output 1=input |
| 278 | pnp_write_config(GPIO_DEV, 0xe1, 0x1); //set output val |
| 279 | pnp_write_config(GPIO_DEV, 0xe2, 0x0); //no inversion |
| 280 | pnp_write_config(GPIO_DEV, 0xe3, 0x3); //0000 0011 0=output 1=input |
| 281 | pnp_write_config(GPIO_DEV, 0xe4, 0xa4); //set output val |
| 282 | //0x10 seems to control something with SGD VIA |
| 283 | |
| 284 | pnp_write_config(GPIO_DEV, 0xe5, 0x0); //no inversion |
| 285 | pnp_write_config(GPIO_DEV, 0x30, 0x9); //Enable GPIO 2 & GPIO 5 |
| 286 | pnp_exit_ext_func_mode(GPIO_DEV); |
| 287 | |
| 288 | |
| 289 | w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); |
| 290 | uart_init(); |
| 291 | console_init(); |
| 292 | |
| 293 | print_info("now booting... real_main\r\n"); |
| 294 | |
| 295 | if (bist == 0) { |
| 296 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 297 | } |
| 298 | /* Halt if there was a built in self test failure */ |
| 299 | report_bist_failure(bist); |
| 300 | setup_default_resource_map(); |
| 301 | setup_coherent_ht_domain(); |
| 302 | wait_all_core0_started(); |
| 303 | print_info("now booting... Core0 started\r\n"); |
| 304 | |
| 305 | #if CONFIG_LOGICAL_CPUS==1 |
| 306 | // It is said that we should start core1 after all core0 launched |
| 307 | start_other_cores(); |
| 308 | wait_all_other_cores_started(bsp_apicid); |
| 309 | #endif |
| 310 | init_timer(); |
| 311 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 312 | needs_reset = optimize_link_coherent_ht(); |
| 313 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 314 | |
| 315 | /* Fixme it assumes that 1000MHz LDT is selected. */ |
| 316 | needs_reset |= k8t890_early_setup_car(16, 0x6); |
| 317 | |
| 318 | if (needs_reset) { |
| 319 | print_debug("ht reset -\r\n"); |
| 320 | soft_reset(); |
| 321 | } |
| 322 | /* stop the APs so we can start them later in init */ |
| 323 | allow_all_aps_stop(bsp_apicid); |
| 324 | /* It's the time to set ctrl now; */ |
| 325 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 326 | enable_smbus(); |
| 327 | memreset_setup(); |
| 328 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 329 | post_cache_as_ram(); |
| 330 | } |
| 331 | |