Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
Ronald G. Minnich | 01b4383 | 2013-08-05 17:18:44 -0700 | [diff] [blame^] | 5 | * Copyright (C) 2012 Samsung Electronics |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 21 | #include <stdlib.h> |
| 22 | #include <string.h> |
| 23 | #include <stddef.h> |
| 24 | #include <delay.h> |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 25 | #include <console/console.h> |
| 26 | #include <device/device.h> |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 27 | #include <cbmem.h> |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 28 | #include <arch/cache.h> |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 29 | #include "fimd.h" |
| 30 | #include "dp-core.h" |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 31 | #include "cpu.h" |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 32 | #include "clk.h" |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 33 | #include "usb.h" |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 34 | #include "chip.h" |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 35 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 36 | static unsigned int cpu_id; |
| 37 | static unsigned int cpu_rev; |
| 38 | |
Ronald G. Minnich | 01b4383 | 2013-08-05 17:18:44 -0700 | [diff] [blame^] | 39 | /* Setting TZPC[TrustZone Protection Controller] */ |
| 40 | static void tzpc_init(void) |
| 41 | { |
| 42 | struct exynos_tzpc *tzpc; |
| 43 | unsigned int addr; |
| 44 | |
| 45 | for (addr = TZPC0_BASE; addr <= TZPC9_BASE; addr += TZPC_BASE_OFFSET) { |
| 46 | tzpc = (struct exynos_tzpc *)addr; |
| 47 | |
| 48 | if (addr == TZPC0_BASE) |
| 49 | writel(R0SIZE, &tzpc->r0size); |
| 50 | |
| 51 | writel(DECPROTXSET, &tzpc->decprot0set); |
| 52 | writel(DECPROTXSET, &tzpc->decprot1set); |
| 53 | |
| 54 | if (addr != TZPC9_BASE) { |
| 55 | writel(DECPROTXSET, &tzpc->decprot2set); |
| 56 | writel(DECPROTXSET, &tzpc->decprot3set); |
| 57 | } |
| 58 | } |
| 59 | } |
| 60 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 61 | static void set_cpu_id(void) |
| 62 | { |
| 63 | cpu_id = readl((void *)EXYNOS_PRO_ID); |
| 64 | cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12)); |
| 65 | |
| 66 | /* |
| 67 | * 0xC200: EXYNOS4210 EVT0 |
| 68 | * 0xC210: EXYNOS4210 EVT1 |
| 69 | */ |
| 70 | if (cpu_id == 0xC200) { |
| 71 | cpu_id |= 0x10; |
| 72 | cpu_rev = 0; |
| 73 | } else if (cpu_id == 0xC210) { |
| 74 | cpu_rev = 1; |
| 75 | } |
| 76 | } |
| 77 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 78 | /* we distinguish a display port device from a raw graphics device |
| 79 | * because there are dramatic differences in startup depending on |
| 80 | * graphics usage. To make startup fast and easier to understand and |
| 81 | * debug we explicitly name this common case. The alternate approach, |
| 82 | * involving lots of machine and callbacks, is hard to debug and |
| 83 | * verify. |
| 84 | */ |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 85 | static void exynos_displayport_init(device_t dev, u32 lcdbase, |
| 86 | unsigned long fb_size) |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 87 | { |
| 88 | int ret; |
| 89 | struct cpu_samsung_exynos5250_config *conf = dev->chip_info; |
| 90 | /* put these on the stack. If, at some point, we want to move |
| 91 | * this code to a pre-ram stage, it will be much easier. |
| 92 | */ |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 93 | struct exynos5_fimd_panel panel; |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 94 | memset(&panel, 0, sizeof(panel)); |
| 95 | |
| 96 | panel.is_dp = 1; /* Display I/F is eDP */ |
| 97 | /* while it is true that we did a memset to zero, |
| 98 | * we leave some 'set to zero' entries here to make |
| 99 | * it clear what's going on. Graphics is confusing. |
| 100 | */ |
| 101 | panel.is_mipi = 0; |
| 102 | panel.fixvclk = 0; |
| 103 | panel.ivclk = 0; |
| 104 | panel.clkval_f = conf->clkval_f; |
| 105 | panel.upper_margin = conf->upper_margin; |
| 106 | panel.lower_margin = conf->lower_margin; |
| 107 | panel.vsync = conf->vsync; |
| 108 | panel.left_margin = conf->left_margin; |
| 109 | panel.right_margin = conf->right_margin; |
| 110 | panel.hsync = conf->hsync; |
Ronald G. Minnich | d83c117 | 2013-04-18 16:10:29 -0700 | [diff] [blame] | 111 | panel.xres = conf->xres; |
| 112 | panel.yres = conf->yres; |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 113 | |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 114 | printk(BIOS_SPEW, "LCD framebuffer @%p\n", (void *)(lcdbase)); |
Gabe Black | 39fda6d | 2013-05-18 23:06:47 -0700 | [diff] [blame] | 115 | memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ |
| 116 | |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 117 | /* |
| 118 | * We need to clean and invalidate the framebuffer region and disable |
| 119 | * caching as well. We assume that our dcache <--> memory address |
| 120 | * space is identity-mapped in 1MB chunks, so align accordingly. |
| 121 | * |
| 122 | * Note: We may want to do something clever to ensure the framebuffer |
| 123 | * region is aligned such that we don't change dcache policy for other |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 124 | * stuff inadvertently. |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 125 | */ |
| 126 | uint32_t lower = ALIGN_DOWN(lcdbase, MiB); |
Gabe Black | 1e797bd | 2013-05-18 15:58:46 -0700 | [diff] [blame] | 127 | uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB); |
Ronald G. Minnich | 2810afa | 2013-04-18 18:09:24 -0700 | [diff] [blame] | 128 | |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 129 | dcache_clean_invalidate_by_mva(lower, upper - lower); |
| 130 | mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); |
| 131 | |
| 132 | printk(BIOS_DEBUG, "Initializing Exynos LCD.\n"); |
| 133 | |
Gabe Black | 1e797bd | 2013-05-18 15:58:46 -0700 | [diff] [blame] | 134 | ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 135 | } |
| 136 | |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 137 | static void cpu_enable(device_t dev) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 138 | { |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 139 | unsigned long fb_size = FB_SIZE_KB * KiB; |
| 140 | u32 lcdbase = get_fb_base_kb() * KiB; |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 141 | |
Stefan Reinauer | 6628744 | 2013-06-19 15:54:19 -0700 | [diff] [blame] | 142 | ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); |
| 143 | mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); |
| 144 | |
| 145 | exynos_displayport_init(dev, lcdbase, fb_size); |
Stefan Reinauer | 043eb0e | 2013-05-10 16:21:58 -0700 | [diff] [blame] | 146 | |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 147 | set_cpu_id(); |
Ronald G. Minnich | 01b4383 | 2013-08-05 17:18:44 -0700 | [diff] [blame^] | 148 | |
| 149 | tzpc_init(); |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | static void cpu_init(device_t dev) |
| 153 | { |
Stefan Reinauer | 08dc357 | 2013-05-14 16:57:50 -0700 | [diff] [blame] | 154 | printk(BIOS_INFO, "CPU: S5P%X @ %ldMHz\n", |
| 155 | cpu_id, get_arm_clk() / (1024*1024)); |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 156 | |
| 157 | usb_init(dev); |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | static void cpu_noop(device_t dev) |
| 161 | { |
| 162 | } |
| 163 | |
| 164 | static struct device_operations cpu_ops = { |
| 165 | .read_resources = cpu_noop, |
| 166 | .set_resources = cpu_noop, |
Stefan Reinauer | 2ad63c2 | 2013-05-17 11:52:45 -0700 | [diff] [blame] | 167 | .enable_resources = cpu_enable, |
| 168 | .init = cpu_init, |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 169 | .scan_bus = 0, |
| 170 | }; |
| 171 | |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 172 | static void enable_exynos5250_dev(device_t dev) |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 173 | { |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 174 | dev->ops = &cpu_ops; |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | struct chip_operations cpu_samsung_exynos5250_ops = { |
| 178 | CHIP_NAME("CPU Samsung Exynos 5250") |
Ronald G. Minnich | b48605d | 2013-04-09 14:35:35 -0700 | [diff] [blame] | 179 | .enable_dev = enable_exynos5250_dev, |
David Hendricks | 6802dc8 | 2013-02-15 16:18:28 -0800 | [diff] [blame] | 180 | }; |
David Hendricks | c01d138 | 2013-03-28 19:04:58 -0700 | [diff] [blame] | 181 | |
| 182 | void exynos5250_config_l2_cache(void) |
| 183 | { |
| 184 | uint32_t val; |
| 185 | |
| 186 | /* |
| 187 | * Bit 9 - L2 tag RAM setup (1 cycle) |
| 188 | * Bits 8:6 - L2 tag RAM latency (3 cycles) |
| 189 | * Bit 5 - L2 data RAM setup (1 cycle) |
| 190 | * Bits 2:0 - L2 data RAM latency (3 cycles) |
| 191 | */ |
| 192 | val = (1 << 9) | (0x2 << 6) | (1 << 5) | (0x2); |
| 193 | write_l2ctlr(val); |
| 194 | } |