skl mainboards/dt: Move genx_dec settings into LPC device scope
Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83172
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index 51cb89a..7a77e64 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -26,9 +26,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- register "gen1_dec" = "0x000c0681"
- register "gen2_dec" = "0x000c1641"
-
# Disable DPTF
register "dptf_enable" = "0"
@@ -114,6 +111,9 @@
device ref pcie_rp4 on end
device ref pcie_rp9 on end
device ref lpc_espi on
+ register "gen1_dec" = "0x000c0681"
+ register "gen2_dec" = "0x000c1641"
+
chip ec/51nb/npce985la0dx
device pnp 0c09.0 on end
device pnp 4e.5 on end
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 609e181..854b887 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -18,11 +18,6 @@
register "lpc_iod" = "0x0070"
register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66"
- # CPLD host command ranges are in 0x280-0x2BF
- # EC PNP registers are at 0x6e and 0x6f
- register "gen1_dec" = "0x003c0281"
- register "gen3_dec" = "0x0004006d"
-
# LPC serial IRQ
register "serirq_mode" = "SERIRQ_CONTINUOUS"
@@ -221,6 +216,11 @@
device ref uart0 on end
device ref emmc on end
device ref lpc_espi on
+ # CPLD host command ranges are in 0x280-0x2BF
+ # EC PNP registers are at 0x6e and 0x6f
+ register "gen1_dec" = "0x003c0281"
+ register "gen3_dec" = "0x0004006d"
+
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index e6a4178..38d0742 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -29,12 +29,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
# FSP Configuration
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"
@@ -379,6 +373,12 @@
end
device ref emmc on end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
chip ec/google/chromeec
device pnp 0c09.0 on end
end
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index a6ec6b6..7d11653 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -52,12 +52,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -407,6 +401,12 @@
end
device ref sdxc on end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
chip ec/google/chromeec
device pnp 0c09.0 on end
end
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 864d73e5..88b7fbc 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -27,10 +27,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -97,6 +93,10 @@
device ref uart0 on end
device ref emmc on end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 8b821f6..85a1e23a 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -27,12 +27,6 @@
register "gpe0_dw1" = "GPP_B"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -363,6 +357,12 @@
device ref sdio off end
device ref sdxc off end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
chip ec/google/chromeec
device pnp 0c09.0 on end
end
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 8fbed5a..c44b380 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -18,12 +18,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -372,6 +366,12 @@
device ref sdio off end
device ref sdxc on end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
chip ec/google/chromeec
device pnp 0c09.0 on end
end
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index c851c37..43c1b4b 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -27,12 +27,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -463,6 +457,12 @@
device ref sdio off end
device ref sdxc off end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
chip ec/google/chromeec
device pnp 0c09.0 on end
end
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 122fb15..5d31208 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -27,12 +27,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -410,6 +404,12 @@
device ref sdio off end
device ref sdxc on end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
chip ec/google/chromeec
device pnp 0c09.0 on end
end
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 140f5f8..9853f49 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -20,12 +20,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -401,6 +395,12 @@
device ref sdio off end
device ref sdxc off end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
chip ec/google/chromeec
device pnp 0c09.0 on end
end
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 823df7c..fa57537 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -27,12 +27,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -376,6 +370,12 @@
device ref sdio off end
device ref sdxc on end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
chip ec/google/chromeec
device pnp 0c09.0 on end
end
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index e877260..d7dea15 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -27,12 +27,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
- # EC memory map range is 0x900-0x9ff
- register "gen3_dec" = "0x00fc0901"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -355,6 +349,12 @@
device ref sdio off end
device ref sdxc on end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
chip ec/google/chromeec
device pnp 0c09.0 on end
end
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index b57deff..be5ba44 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -13,9 +13,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -127,6 +124,10 @@
device ref emmc on end
device ref sdxc on end
device ref smbus on end
+ device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ end
device ref fast_spi on end
end
end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 81557eb..0af8282 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -3,9 +3,6 @@
# GPE configuration
register "gpe0_dw0" = "GPP_C"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen2_dec" = "0x000c0201"
-
# FSP Configuration
register "DspEnable" = "1"
@@ -123,6 +120,9 @@
device ref pcie_rp9 on end # x1 WLAN
device ref pcie_rp10 on end # x1 WIGIG
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen2_dec" = "0x000c0201"
+
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index 9e8c814..87bf0d8 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -10,9 +10,6 @@
register "deep_s5_enable_ac" = "1"
register "deep_s5_enable_dc" = "1"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen2_dec" = "0x000c0201"
-
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
@@ -164,6 +161,9 @@
device ref pcie_rp5 on end
device ref pcie_rp6 on end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen2_dec" = "0x000c0201"
+
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 45f7103..6e08059 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -13,10 +13,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
- register "gen1_dec" = "0x00fc0801"
- register "gen2_dec" = "0x000c0201"
-
# Enable DPTF
register "dptf_enable" = "1"
@@ -235,6 +231,10 @@
device ref emmc on end
device ref sdxc on end
device ref lpc_espi on
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index d6bc990..f173e1e 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -25,10 +25,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f
- register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef
- register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff
-
# Disable DPTF
register "dptf_enable" = "0"
@@ -173,6 +169,9 @@
device ref pcie_rp11 on end
device ref pcie_rp12 on end
device ref lpc_espi on
+ register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f
+ register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef
+ register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index 6148196..0b5d0cd 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -12,11 +12,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- register "gen1_dec" = "0x00fc0201"
- register "gen2_dec" = "0x007c0a01"
- register "gen3_dec" = "0x000c03e1"
- register "gen4_dec" = "0x001c02e1"
-
register "eist_enable" = "1"
# Disable DPTF
@@ -202,6 +197,10 @@
"SlotLengthShort" "WIFI1" "SlotDataBusWidth1X"
end
device ref lpc_espi on
+ register "gen1_dec" = "0x00fc0201"
+ register "gen2_dec" = "0x007c0a01"
+ register "gen3_dec" = "0x000c03e1"
+ register "gen4_dec" = "0x001c02e1"
chip superio/ite/it8772f
register "TMPIN1.mode" = "THERMAL_RESISTOR"
register "TMPIN2.mode" = "THERMAL_RESISTOR"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 03d48fa..5b222fc 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -34,9 +34,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
- register "gen1_dec" = "0x00000381"
-
# Disable DPTF
register "dptf_enable" = "0"
@@ -153,6 +150,8 @@
device ref pcie_rp5 on end
device ref pcie_rp9 on end
device ref lpc_espi on
+ # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
+ register "gen1_dec" = "0x00000381"
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index da44d22..438d323 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -15,9 +15,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- register "gen1_dec" = "0x000c0681"
- register "gen2_dec" = "0x000c1641"
-
# Disable DPTF
register "dptf_enable" = "0"
@@ -175,6 +172,9 @@
device ref pcie_rp5 on end
device ref pcie_rp9 on end
device ref lpc_espi on
+ register "gen1_dec" = "0x000c0681"
+ register "gen2_dec" = "0x000c1641"
+
chip superio/ite/it8528e
device pnp 6e.1 off end
device pnp 6e.2 off end
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
index 4063bed..8a28ca1 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/overridetree.cb
@@ -8,9 +8,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- register "gen1_dec" = "0x007c0a01" # Super IO SWC
- register "gen2_dec" = "0x000c0ca1" # IPMI KCS
-
# Additional FSP Configuration
# This board has an IGD with no output.
register "PrimaryDisplay" = "Display_Auto"
@@ -83,6 +80,9 @@
smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
end
device ref lpc_espi on
+ register "gen1_dec" = "0x007c0a01" # Super IO SWC
+ register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+
chip drivers/ipmi
# On cold boot it takes a while for the BMC to start the IPMI service
register "wait_for_bmc" = "1"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
index 035811f..97f995d 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
@@ -8,9 +8,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- register "gen1_dec" = "0x007c0a01" # Super IO SWC
- register "gen2_dec" = "0x000c0ca1" # IPMI KCS
-
# FIXME: find out why FSP crashes without this
register "PchHdaVcType" = "Vc1"
@@ -67,6 +64,9 @@
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
end
device ref lpc_espi on
+ register "gen1_dec" = "0x007c0a01" # Super IO SWC
+ register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+
chip drivers/ipmi
use pch_gpio as gpio_dev
register "post_complete_gpio" = "GPP_B20"
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
index 1b553d1..7993383 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
@@ -8,9 +8,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- register "gen1_dec" = "0x007c0a01" # Super IO SWC
- register "gen2_dec" = "0x000c0ca1" # IPMI KCS
-
device domain 0 on
subsystemid 0x15d9 0x0896 inherit
device ref south_xhci on
@@ -84,6 +81,9 @@
end
end
device ref lpc_espi on
+ register "gen1_dec" = "0x007c0a01" # Super IO SWC
+ register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+
chip drivers/ipmi
use pch_gpio as gpio_dev
register "bmc_jumper_gpio" = "GPP_D22" # JPB1
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
index 17ba31b..1d0dc7f 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssw-f/overridetree.cb
@@ -8,9 +8,6 @@
register "gpe0_dw1" = "GPP_D"
register "gpe0_dw2" = "GPP_E"
- register "gen1_dec" = "0x007c0a01" # Super IO SWC
- register "gen2_dec" = "0x000c0ca1" # IPMI KCS
-
# Additional FSP Configuration
# This board has an IGD with no output.
register "PrimaryDisplay" = "Display_Auto"
@@ -71,6 +68,9 @@
end
end
device ref lpc_espi on
+ register "gen1_dec" = "0x007c0a01" # Super IO SWC
+ register "gen2_dec" = "0x000c0ca1" # IPMI KCS
+
chip drivers/ipmi
# On cold boot it takes a while for the BMC to start the IPMI service
register "wait_for_bmc" = "1"