| chip soc/intel/skylake |
| |
| # IGD Displays |
| register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| |
| # Deep Sx states |
| register "deep_s3_enable_ac" = "0" |
| register "deep_s3_enable_dc" = "0" |
| register "deep_s5_enable_ac" = "1" |
| register "deep_s5_enable_dc" = "1" |
| register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" |
| |
| register "eist_enable" = "1" |
| |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route. i.e. If this route changes then the affected GPE |
| # offset bits also need to be changed. |
| register "gpe0_dw0" = "GPP_C" |
| register "gpe0_dw1" = "GPP_D" |
| register "gpe0_dw2" = "GPP_E" |
| |
| # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| register "gen1_dec" = "0x00fc0801" |
| register "gen2_dec" = "0x000c0201" |
| # EC memory map range is 0x900-0x9ff |
| register "gen3_dec" = "0x00fc0901" |
| |
| # Enable DPTF |
| register "dptf_enable" = "1" |
| |
| # Enable S0ix |
| register "s0ix_enable" = true |
| |
| # Disable Command TriState |
| register "CmdTriStateDis" = "1" |
| |
| # FSP Configuration |
| register "DspEnable" = "1" |
| register "IoBufferOwnership" = "3" |
| register "ScsEmmcHs400Enabled" = "1" |
| register "SkipExtGfxScan" = "1" |
| register "SaGv" = "SaGv_Enabled" |
| register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| register "PmConfigSlpS4MinAssert" = "1" # 1s |
| register "PmConfigSlpSusMinAssert" = "1" # 500ms |
| register "PmConfigSlpAMinAssert" = "3" # 2s |
| |
| register "power_limits_config" = "{ |
| .tdp_pl1_override = 7, |
| .tdp_pl2_override = 18, |
| .psys_pmax = 45, |
| }" |
| register "tcc_offset" = "10" |
| |
| # VR Settings Configuration for 4 Domains |
| #+----------------+-------+-------+-------+-------+ |
| #| Domain/Setting | SA | IA | GTUS | GTS | |
| #+----------------+-------+-------+-------+-------+ |
| #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| #| Psi2Threshold | 2A | 2A | 2A | 2A | |
| #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| #| Psi3Enable | 1 | 1 | 1 | 1 | |
| #| Psi4Enable | 1 | 1 | 1 | 1 | |
| #| ImonSlope | 0 | 0 | 0 | 0 | |
| #| ImonOffset | 0 | 0 | 0 | 0 | |
| #| IccMax | Set by SoC code per CPU SKU | |
| #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| #| AcLoadline | 14.9 | 4 | 5.7 | 4.57 | |
| #| DcLoadline | 14.2 | 4 | 4.2 | 4.3 | |
| #+----------------+-------+-------+-------+-------+ |
| register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(2), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .voltage_limit = 1520, |
| .ac_loadline = 1490, |
| .dc_loadline = 1420, |
| }" |
| |
| register "domain_vr_config[VR_IA_CORE]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(2), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .voltage_limit = 1520, |
| .ac_loadline = 400, |
| .dc_loadline = 400, |
| }" |
| |
| register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(2), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .voltage_limit = 1520, |
| .ac_loadline = 570, |
| .dc_loadline = 420, |
| }" |
| |
| register "domain_vr_config[VR_GT_SLICED]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(2), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .voltage_limit = 1520, |
| .ac_loadline = 457, |
| .dc_loadline = 430, |
| }" |
| |
| # PCIe Root port 1 with SRCCLKREQ1# |
| register "PcieRpEnable[0]" = "1" |
| register "PcieRpClkReqSupport[0]" = "1" |
| register "PcieRpClkReqNumber[0]" = "1" |
| register "PcieRpClkSrcNumber[0]" = "1" |
| register "PcieRpAdvancedErrorReporting[0]" = "1" |
| register "PcieRpLtrEnable[0]" = "1" |
| |
| # Root port 9 (x2) |
| # PcieRpEnable: Enable root port |
| # PcieRpClkReqSupport: Enable CLKREQ# |
| # PcieRpClkReqNumber: Uses SRCCLKREQ2# |
| # PcieRpClkSrcNumber: Uses 3 |
| # PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting |
| # PcieRpLtrEnable: Enable Latency Tolerance Reporting Mechanism |
| register "PcieRpEnable[8]" = "1" |
| register "PcieRpClkReqSupport[8]" = "1" |
| register "PcieRpClkReqNumber[8]" = "2" |
| register "PcieRpClkSrcNumber[8]" = "3" |
| register "PcieRpAdvancedErrorReporting[8]" = "1" |
| register "PcieRpLtrEnable[8]" = "1" |
| |
| # Intel Common SoC Config |
| #+-------------------+---------------------------+ |
| #| Field | Value | |
| #+-------------------+---------------------------+ |
| #| GSPI0 | cr50 TPM. Early init is | |
| #| | required to set up a BAR | |
| #| | for TPM communication | |
| #| | before memory is up | |
| #| I2C0 | Touchscreen | |
| #| I2C1 | Trackpad | |
| #| I2C3 | Camera | |
| #| I2C4 | Audio | |
| #| I2C5 | Rear Camera & SAR | |
| #| pch_thermal_trip | PCH Trip Temperature | |
| #+-------------------+---------------------------+ |
| register "common_soc_config" = "{ |
| .i2c[0] = { |
| .speed = I2C_SPEED_FAST, |
| .rise_time_ns = 98, |
| .fall_time_ns = 38, |
| }, |
| .i2c[1] = { |
| .speed = I2C_SPEED_FAST, |
| .speed_config[0] = { |
| .speed = I2C_SPEED_FAST, |
| .scl_lcnt = 186, |
| .scl_hcnt = 93, |
| .sda_hold = 36, |
| }, |
| }, |
| .i2c[3] = { |
| .speed = I2C_SPEED_FAST, |
| .rise_time_ns = 98, |
| .fall_time_ns = 38, |
| }, |
| .i2c[4] = { |
| .speed = I2C_SPEED_FAST, |
| .speed_config[0] = { |
| .speed = I2C_SPEED_FAST, |
| .scl_lcnt = 176, |
| .scl_hcnt = 95, |
| .sda_hold = 36, |
| } |
| }, |
| .i2c[5] = { |
| .speed = I2C_SPEED_FAST, |
| .rise_time_ns = 98, |
| .fall_time_ns = 38, |
| }, |
| .gspi[0] = { |
| .speed_mhz = 1, |
| .early_init = 1, |
| }, |
| .pch_thermal_trip = 75, |
| }" |
| # Touchscreen |
| register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" |
| |
| # Trackpad |
| register "i2c_voltage[1]" = "I2C_VOLTAGE_1V8" |
| |
| # Front Camera |
| register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" |
| |
| # Audio |
| register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" |
| |
| # Rear Camera & SAR |
| register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" |
| |
| register "SerialIoDevMode" = "{ |
| [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C3] = PchSerialIoPci, |
| [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| [PchSerialIoIndexI2C5] = PchSerialIoPci, |
| [PchSerialIoIndexSpi0] = PchSerialIoPci, |
| [PchSerialIoIndexSpi1] = PchSerialIoPci, |
| [PchSerialIoIndexUart0] = PchSerialIoSkipInit, |
| [PchSerialIoIndexUart1] = PchSerialIoDisabled, |
| [PchSerialIoIndexUart2] = PchSerialIoSkipInit, |
| }" |
| |
| device domain 0 on |
| device ref system_agent on end |
| device ref igpu on end |
| device ref sa_thermal on end |
| device ref imgu on end |
| device ref south_xhci on |
| register "usb2_ports" = "{ |
| [0] = USB2_PORT_LONG(OC0), // Type-C Port 1 |
| [2] = USB2_PORT_SHORT(OC_SKIP), // Bluetooth |
| [4] = USB2_PORT_LONG(OC1), // Type-C Port 2 |
| [6] = USB2_PORT_LONG(OC_SKIP), // pogo port |
| }" |
| |
| register "usb3_ports" = "{ |
| [0] = USB3_PORT_DEFAULT(OC0), // Type-C Port 1 |
| [1] = USB3_PORT_DEFAULT(OC1), // Type-C Port 2 |
| }" |
| |
| chip drivers/usb/acpi |
| register "desc" = ""Root Hub"" |
| register "type" = "UPC_TYPE_HUB" |
| device usb 0.0 on |
| chip drivers/usb/acpi |
| register "desc" = ""USB Type C Port 1"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| device usb 2.0 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""Bluetooth"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E2)" |
| device usb 2.2 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB Type C Port 2"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| device usb 2.4 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""POGO"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device usb 2.6 on end |
| end |
| end |
| end |
| end |
| device ref south_xdci on end |
| device ref thermal on end |
| device ref cio on end |
| device ref i2c0 on |
| chip drivers/i2c/hid |
| register "generic.hid" = ""WCOM50C1"" |
| register "generic.desc" = ""WCOM Digitizer"" |
| register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" |
| register "generic.speed" = "I2C_SPEED_FAST_PLUS" |
| register "generic.detect" = "1" |
| register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E11)" |
| register "generic.reset_delay_ms" = "20" |
| register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" |
| register "generic.enable_delay_ms" = "1" |
| register "generic.has_power_resource" = "1" |
| register "hid_desc_reg_offset" = "0x1" |
| device i2c 0a on end |
| end |
| end |
| device ref i2c1 on |
| chip drivers/i2c/sx9310 |
| register "desc" = ""Right SAR Proximity Sensor"" |
| register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" |
| register "speed" = "I2C_SPEED_FAST" |
| register "uid" = "0" |
| device i2c 28 on end |
| register "cs0_ground" = "0x0" |
| register "combined_sensors_count" = "3" |
| register "combined_sensors[0]" = "0" |
| register "combined_sensors[1]" = "1" |
| register "combined_sensors[2]" = "2" |
| register "resolution" = "SX9310_FINEST" |
| register "avg_pos_strength" = "512" |
| register "startup_sensor" = "0" |
| register "proxraw_strength" = "0" |
| end |
| end |
| device ref i2c2 off end |
| device ref i2c3 on end |
| device ref heci1 on end |
| device ref heci2 off end |
| device ref csme_ider off end |
| device ref csme_ktr off end |
| device ref heci3 off end |
| device ref sata off end |
| device ref uart2 on end |
| device ref i2c5 on |
| chip drivers/i2c/sx9310 |
| register "desc" = ""Left SAR Proximity Sensor"" |
| register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D10_IRQ)" |
| register "speed" = "I2C_SPEED_FAST" |
| register "uid" = "1" |
| device i2c 28 on end |
| register "cs0_ground" = "0x0" |
| register "combined_sensors_count" = "3" |
| register "combined_sensors[0]" = "0" |
| register "combined_sensors[1]" = "1" |
| register "combined_sensors[2]" = "2" |
| register "resolution" = "SX9310_FINEST" |
| register "avg_pos_strength" = "512" |
| register "startup_sensor" = "0" |
| register "proxraw_strength" = "0" |
| end |
| end |
| device ref i2c4 on |
| chip drivers/i2c/max98373 |
| register "vmon_slot_no" = "4" |
| register "imon_slot_no" = "5" |
| register "uid" = "0" |
| register "desc" = ""RIGHT SPEAKER AMP"" |
| register "name" = ""MAXR"" |
| device i2c 32 on end |
| end |
| chip drivers/i2c/max98373 |
| register "vmon_slot_no" = "6" |
| register "imon_slot_no" = "7" |
| register "uid" = "1" |
| register "desc" = ""LEFT SPEAKER AMP"" |
| register "name" = ""MAXL"" |
| device i2c 31 on end |
| end |
| end |
| device ref pcie_rp1 on |
| chip drivers/wifi/generic |
| register "wake" = "GPE0_DW2_01" |
| device pci 00.0 on end |
| end |
| end |
| device ref pcie_rp2 off end |
| device ref pcie_rp3 off end |
| device ref pcie_rp4 off end |
| device ref pcie_rp5 off end |
| device ref pcie_rp6 off end |
| device ref pcie_rp7 off end |
| device ref pcie_rp8 off end |
| device ref pcie_rp9 on end |
| device ref pcie_rp10 off end |
| device ref pcie_rp11 off end |
| device ref pcie_rp12 off end |
| device ref uart0 off end |
| device ref uart1 off end |
| device ref gspi0 on |
| chip drivers/spi/acpi |
| register "hid" = "ACPI_DT_NAMESPACE_HID" |
| register "compat_string" = ""google,cr50"" |
| register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" |
| device spi 0 on end |
| end |
| end |
| device ref gspi1 on |
| chip drivers/spi/acpi |
| register "name" = ""CRFP"" |
| register "hid" = "ACPI_DT_NAMESPACE_HID" |
| register "uid" = "1" |
| register "compat_string" = ""google,cros-ec-spi"" |
| register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)" |
| register "wake" = "GPE0_DW0_09" # GPP_C9 |
| device spi 0 on end |
| end # FPMCU |
| end |
| device ref emmc on end |
| device ref sdio off end |
| device ref sdxc off end |
| device ref lpc_espi on |
| chip ec/google/chromeec |
| device pnp 0c09.0 on end |
| end |
| end |
| device ref p2sb on end |
| device ref pmc on end |
| device ref hda on end |
| device ref smbus on end |
| device ref fast_spi on end |
| device ref gbe off end |
| end |
| end |