| chip soc/intel/skylake |
| |
| # Enable deep Sx states |
| register "deep_s3_enable_ac" = "0" |
| register "deep_s3_enable_dc" = "0" |
| register "deep_s5_enable_ac" = "1" |
| register "deep_s5_enable_dc" = "1" |
| register "deep_sx_config" = "DSX_EN_WAKE_PIN" |
| |
| register "eist_enable" = "1" |
| |
| register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| |
| # Set the Thermal Control Circuit (TCC) activation value to 95C |
| # even though FSP integration guide says to set it to 100C for SKL-U |
| # (offset at 0), because when the TCC activates at 100C, the CPU |
| # will have already shut itself down from overheating protection. |
| register "tcc_offset" = "5" # TCC of 95C |
| |
| # GPE configuration |
| # Note that GPE events called out in ASL code rely on this |
| # route. i.e. If this route changes then the affected GPE |
| # offset bits also need to be changed. |
| register "gpe0_dw0" = "GPP_C" |
| register "gpe0_dw1" = "GPP_D" |
| register "gpe0_dw2" = "GPP_E" |
| |
| # Disable DPTF |
| register "dptf_enable" = "0" |
| |
| # FSP Configuration |
| register "SataPortsEnable" = "{ |
| [0] = 1, |
| [1] = 1, |
| [2] = 1, |
| }" |
| register "SataSpeedLimit" = "2" |
| register "DspEnable" = "1" |
| register "IoBufferOwnership" = "0" |
| register "SkipExtGfxScan" = "1" |
| register "SaGv" = "SaGv_Enabled" |
| register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| register "PmConfigSlpS4MinAssert" = "1" # 1s |
| register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| register "PmConfigSlpAMinAssert" = "3" # 2s |
| |
| # VR Settings Configuration for 4 Domains |
| #+----------------+-------+-------+-------------+-------+ |
| #| Domain/Setting | SA | IA | GT-Unsliced | GT | |
| #+----------------+-------+-------+-------------+-------+ |
| #| Psi1Threshold | 20A | 20A | 20A | 20A | |
| #| Psi2Threshold | 4A | 5A | 5A | 5A | |
| #| Psi3Threshold | 1A | 1A | 1A | 1A | |
| #| Psi3Enable | 1 | 1 | 1 | 1 | |
| #| Psi4Enable | 1 | 1 | 1 | 1 | |
| #| ImonSlope | 0 | 0 | 0 | 0 | |
| #| ImonOffset | 0 | 0 | 0 | 0 | |
| #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | |
| #+----------------+-------+-------+-------------+-------+ |
| register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(4), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .voltage_limit = 1520, |
| }" |
| |
| register "domain_vr_config[VR_IA_CORE]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(5), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .voltage_limit = 1520, |
| }" |
| |
| register "domain_vr_config[VR_GT_UNSLICED]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(5), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .voltage_limit = 1520, |
| }" |
| |
| register "domain_vr_config[VR_GT_SLICED]" = "{ |
| .vr_config_enable = 1, |
| .psi1threshold = VR_CFG_AMP(20), |
| .psi2threshold = VR_CFG_AMP(5), |
| .psi3threshold = VR_CFG_AMP(1), |
| .psi3enable = 1, |
| .psi4enable = 1, |
| .imon_slope = 0x0, |
| .imon_offset = 0x0, |
| .voltage_limit = 1520, |
| }" |
| |
| register "PcieRpEnable[2]" = "1" |
| register "PcieRpEnable[3]" = "1" |
| register "PcieRpEnable[4]" = "1" |
| register "PcieRpEnable[8]" = "1" |
| register "PcieRpEnable[9]" = "1" |
| register "PcieRpEnable[10]" = "1" |
| register "PcieRpEnable[11]" = "1" |
| |
| register "PcieRpClkSrcNumber[0]" = "0" |
| register "PcieRpClkSrcNumber[3]" = "1" |
| register "PcieRpClkSrcNumber[4]" = "2" |
| register "PcieRpClkSrcNumber[8]" = "3" |
| register "PcieRpClkSrcNumber[9]" = "3" |
| register "PcieRpClkSrcNumber[10]" = "3" |
| register "PcieRpClkSrcNumber[11]" = "3" |
| |
| # PL2 override 25W |
| register "power_limits_config" = "{ |
| .tdp_pl2_override = 25, |
| }" |
| |
| # Send an extra VR mailbox command for the PS4 exit issue |
| register "SendVrMbxCmd" = "2" |
| |
| device domain 0 on |
| device ref igpu on end |
| device ref sa_thermal on end |
| device ref south_xhci on |
| register "usb2_ports" = "{ |
| [0] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ |
| [1] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (right) */ |
| [2] = USB2_PORT_MID(OC_SKIP), /* WiFi */ |
| [3] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ |
| [4] = USB2_PORT_MID(OC_SKIP), /* F_USB3 header */ |
| [5] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ |
| [6] = USB2_PORT_MID(OC_SKIP), /* Type-A Port (left) */ |
| [7] = USB2_PORT_MID(OC_SKIP), /* GL850G for F_USB1 and F_USB2 headers */ |
| }" |
| |
| register "usb3_ports" = "{ |
| [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ |
| [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A Port (right) */ |
| [2] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ |
| [3] = USB3_PORT_DEFAULT(OC_SKIP), /* F_USB3 header */ |
| }" |
| end |
| device ref south_xdci on end |
| device ref thermal on end |
| device ref heci1 on end |
| device ref sata on end |
| device ref pcie_rp3 on end |
| device ref pcie_rp5 on |
| smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" |
| "SlotLengthOther" "MPCIE_WIFI1" "SlotDataBusWidth1X" |
| end |
| device ref pcie_rp6 on end |
| device ref pcie_rp9 on |
| smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" |
| "SSD_M.2 2242/2280" "SlotDataBusWidth4X" |
| end |
| device ref pcie_rp10 on end |
| device ref pcie_rp11 on end |
| device ref pcie_rp12 on end |
| device ref lpc_espi on |
| register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f |
| register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef |
| register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff |
| chip drivers/pc80/tpm |
| device pnp 0c31.0 on end |
| end |
| chip superio/ite/it8786e |
| register "TMPIN1.mode" = "THERMAL_PECI" |
| register "TMPIN1.offset" = "100" |
| register "TMPIN1.min" = "128" |
| register "TMPIN2.mode" = "THERMAL_RESISTOR" |
| register "TMPIN2.min" = "128" |
| register "TMPIN3.mode" = "THERMAL_MODE_DISABLED" |
| register "ec.vin_mask" = "VIN_ALL" |
| # FAN1 is CPU fan (on board) |
| register "FAN1.mode" = "FAN_SMART_AUTOMATIC" |
| register "FAN1.smart.tmpin" = " 1" |
| register "FAN1.smart.tmp_off" = "35" |
| register "FAN1.smart.tmp_start" = "60" |
| register "FAN1.smart.tmp_full" = "85" |
| register "FAN1.smart.tmp_delta" = " 2" |
| register "FAN1.smart.pwm_start" = "20" |
| register "FAN1.smart.slope" = "24" |
| # FAN2 is system fan (4 pin connector populated) |
| #register "FAN2.mode" = "FAN_MODE_OFF" |
| # FAN3 PWM is used for LVDS backlight control |
| #register "FAN3.mode" = "FAN_MODE_OFF" |
| |
| device pnp 2e.1 on # COM 1 |
| io 0x60 = 0x3f8 |
| irq 0x70 = 4 |
| end |
| device pnp 2e.2 on # COM 2 |
| io 0x60 = 0x2f8 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.3 on # Printer Port |
| io 0x60 = 0x378 |
| io 0x62 = 0x778 |
| irq 0x70 = 5 |
| drq 0x74 = 3 |
| end |
| device pnp 2e.4 on # Environment Controller |
| io 0x60 = 0xa40 |
| io 0x62 = 0xa30 |
| irq 0x70 = 9 |
| end |
| device pnp 2e.5 on # Keyboard |
| io 0x60 = 0x60 |
| io 0x62 = 0x64 |
| irq 0x70 = 1 |
| end |
| device pnp 2e.6 on # Mouse |
| irq 0x70 = 12 |
| end |
| device pnp 2e.7 off # GPIO |
| end |
| device pnp 2e.8 on # COM 3 |
| io 0x60 = 0x3e8 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.9 on # COM 4 |
| io 0x60 = 0x2e8 |
| irq 0x70 = 4 |
| end |
| device pnp 2e.a off end # CIR |
| device pnp 2e.b on # COM 5 |
| io 0x60 = 0x2f0 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.c on # COM 6 |
| io 0x60 = 0x2e0 |
| irq 0x70 = 4 |
| end |
| end |
| end |
| device ref hda on end |
| device ref smbus on end |
| device ref fast_spi on end |
| end |
| end |