Gitiles
Code Review Sign In
review.coreboot.org / coreboot / fbdb085549b6c500e12dc2fb21143a197b4be042 / src / northbridge / intel
  1. fbdb085 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT by Kyösti Mälkki · 11 years ago
  2. 15c4ab7 Move select MMCONF_SUPPORT under northbridge by Kyösti Mälkki · 11 years ago
  3. abe6847 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c` by Paul Menzel · 11 years ago
  4. 1cc3416 Add support to enable/disable builtin GbE (again) by Stefan Reinauer · 11 years ago
  5. 714212a Revert "Add support to enable/disable builtin GbE" by Kyösti Mälkki · 11 years ago
  6. 59fb82a intel/sch: Use MMCONF_BASE_ADDRESS by Kyösti Mälkki · 11 years ago
  7. eac00d2 intel/sandybridge: Locate CBMEM TOC early in ramstage by Kyösti Mälkki · 11 years ago
  8. d358a50 Add support to enable/disable builtin GbE by Stefan Reinauer · 11 years ago
  9. 483ff82 sandybridge: Store MRC cache in CBFS by Patrick Georgi · 11 years ago
  10. 7ed7394 i945: Add Display defines for int15h handler. by Denis 'GNUtoo' Carikli · 11 years ago
  11. fd39ddd Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGS by Denis 'GNUtoo' Carikli · 11 years ago
  12. a296ce7 Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture by Ronald G. Minnich · 11 years ago
  13. 27435d3 haswell: fix overflow handling TOUUD by Aaron Durbin · 11 years ago
  14. 5750fdd Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h` by Ronald G. Minnich · 11 years ago
  15. 51837f9 Intel Sandy Bridge: udelay.c: Change comparison from <= to < by Paul Menzel · 11 years ago
  16. 393619b intel/gm45: Add more debug output to read/write training by Nico Huber · 11 years ago
  17. 12276ac intel/gm45: Handle overflows during DDR3 write training by Nico Huber · 11 years ago
  18. 08bee23 intel/gm45: Refactor DDR3 write training by Nico Huber · 11 years ago
  19. 35e45c0 intel/gm45: Handle overflows during DDR3 read training by Nico Huber · 11 years ago
  20. 26a6435 intel/gm45: Refactor DDR3 read training by Nico Huber · 11 years ago
  21. 0da9286 intel/gm45: Fix interpretation of VT-d disable bit by Nico Huber · 11 years ago
  22. 0f43af2 intel/i5000: Remove unused copy of udelay.c by Nico Huber · 11 years ago
  23. c5e036a Get rid of a number of __GNUC__ checks by Stefan Reinauer · 11 years ago
  24. bed88d6 northbridge/intel/i5000/udelay.c: Remove unused header `console.h` by Paul Menzel · 11 years ago
  25. 3f5f6d8 Drop prototype guarding for romcc by Stefan Reinauer · 11 years ago
  26. 7cb1ba9 haswell: use tsc for udelay() by Aaron Durbin · 11 years ago
  27. 243aa44 boot: remove cbmem_post_handling() by Aaron Durbin · 11 years ago
  28. 4b213a8 Intel i945: ACPI: Add _OSC method by Denis 'GNUtoo' Carikli · 11 years ago
  29. ed7e29e Lenovo ThinkPad X60: Add Native VGA init. by Denis 'GNUtoo' Carikli · 11 years ago
  30. c6f2722 sandybridge: enable ROM caching by Aaron Durbin · 11 years ago
  31. f567f16 sandybridge: add option to mark graphics memory write-combining. by Aaron Durbin · 11 years ago
  32. fcfe67c haswell: add option to mark graphics memory write-combining. by Aaron Durbin · 11 years ago
  33. bb4e79a x86: add new mtrr implementation by Aaron Durbin · 11 years ago
  34. c965076 resources: introduce reserved_ram_resource() by Aaron Durbin · 11 years ago
  35. c0cbd6e haswell: use dynamic cbmem by Aaron Durbin · 11 years ago
  36. dd4a6d2 coreboot: dynamic cbmem requirement by Aaron Durbin · 11 years ago
  37. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 11 years ago
  38. 467f31d haswell/lynxpoint: Use new PCH/PM helper functions by Duncan Laurie · 11 years ago
  39. 969ac8d haswell: Drop the device ID check in graphics init path by Duncan Laurie · 11 years ago
  40. 8ce667e haswell: add multipurpose SMM memory region by Aaron Durbin · 12 years ago
  41. bf396ff haswell: use s3_resume field in romstage_handoff by Aaron Durbin · 12 years ago
  42. 605ca1b haswell: cbmem_get_table_location() implementation by Aaron Durbin · 12 years ago
  43. 0013a69 haswell: drop memory reservation for sandybridge GPU bug by Duncan Laurie · 11 years ago
  44. 2ad1dba haswell: move call site of save_mrc_data() by Aaron Durbin · 12 years ago
  45. 9b7f9b9 haswell: remove unused sys_info structure by Aaron Durbin · 12 years ago
  46. 3d0071b haswell: adjust CAR usage by Aaron Durbin · 12 years ago
  47. 21efd8c haswell: fix ACPI MCFG table by Aaron Durbin · 12 years ago
  48. 7af2069 haswell: enable caching before SMM initialization by Aaron Durbin · 12 years ago
  49. 239c2e8 haswell platforms: restructure romstage main by Aaron Durbin · 12 years ago
  50. e6c3b1d haswell: include TSEG region in cacheable memory by Aaron Durbin · 12 years ago
  51. 86a1110 i945: Replace some two magic values by defined names by Patrick Georgi · 11 years ago
  52. 5c66f08 haswell: don't add a 0-sized memory range resource by Aaron Durbin · 12 years ago
  53. 69efaa0 Google Link: Add remaining code to support native graphics by Ronald G. Minnich · 11 years ago
  54. 1570260 haswell: Fix BDSM and BGSM indicies in memory map by Aaron Durbin · 12 years ago
  55. 1fef1f5 haswell: reserve default SMRAM space by Aaron Durbin · 12 years ago
  56. c12ef97 haswell: resource allocation by Aaron Durbin · 12 years ago
  57. 26e7dd7 haswell: more ULT/LP support and minor tweaks by Duncan Laurie · 12 years ago
  58. 7116129 haswell: Add VGA PCI ID mappings by Aaron Durbin · 12 years ago
  59. df7be71 haswell: Add ULT device IDs by Duncan Laurie · 12 years ago
  60. f72ad02 graysreef: update platform information by Aaron Durbin · 12 years ago
  61. 89f79a0 haswell: remove explicit pcie config accesses by Aaron Durbin · 12 years ago
  62. c1989c4 haswell: add PCI id support by Aaron Durbin · 12 years ago
  63. b6b5aa1 haswell: Remove logic to send dram init done to ME by Aaron Durbin · 12 years ago
  64. 30c3900 haswell: notes and updates. by Aaron Durbin · 12 years ago
  65. 8256a9b haswell: align pei_data structure with intel-framework by Aaron Durbin · 12 years ago
  66. b9adf7b haswell: use #defines for constants in udelay.c by Aaron Durbin · 12 years ago
  67. ce36b12 haswell: Add LPT LP device IDs to platform report by Duncan Laurie · 12 years ago
  68. 67113e9 haswell: Update GPU power management setup by Duncan Laurie · 12 years ago
  69. 6d04f0f haswell: always use MMIO PCI config accesses by Aaron Durbin · 12 years ago
  70. 76c3700 haswell: Add initial support for Haswell platforms by Aaron Durbin · 12 years ago
  71. e7ae96f Add Intel Panther Point USB3 initialization by Marc Jones · 12 years ago
  72. 41dd3db Intel e7505: provide get_top_of_ram by Kyösti Mälkki · 12 years ago
  73. a46a712 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« by Paul Menzel · 11 years ago
  74. fd611f9 Drop CONFIG_WRITE_HIGH_TABLES by Stefan Reinauer · 11 years ago
  75. 0aa37c4 sconfig: rename lapic_cluster -> cpu_cluster by Stefan Reinauer · 12 years ago
  76. 4aff445 sconfig: rename pci_domain -> domain by Stefan Reinauer · 12 years ago
  77. 600784e spi.h: Rename the spi.h to spi-generic.h by Zheng Bao · 12 years ago
  78. 8cc8468 Intel: Replace MSR 0xcd with MSR_FSB_FREQ by Patrick Georgi · 12 years ago
  79. 6fe0cab Extend CBFS to support arbitrary ROM source media. by Hung-Te Lin · 12 years ago
  80. 816e9d1 Support for Celeron 1007U by Stefan Reinauer · 12 years ago
  81. 5079a0d Remove assembly coded log2 function by Ronald G. Minnich · 12 years ago
  82. 721265b Drop driver-y from GM45/ICH9/RK9 by Stefan Reinauer · 12 years ago
  83. e135ac5 Remove AMD special case for LAPIC based udelay() by Patrick Georgi · 12 years ago
  84. 23f38cd Get rid of drivers class by Patrick Georgi · 12 years ago
  85. 2efc880 intel/gm45: new northbridge by Patrick Georgi · 12 years ago
  86. 3c84261 yabel: Use X86_* instead of the more verbose M.x86.REG_* by Patrick Georgi · 12 years ago
  87. 6446626 Use new system agent binaries by Stefan Reinauer · 12 years ago
  88. 313ec9d Sandybridge: Set PEG clock gating by Marc Jones · 12 years ago
  89. 7e8c8e9 Add PCIe init and NMode flag to PEI data structure by Stefan Reinauer · 12 years ago
  90. e8179b5 Add ddr3lv_support flag to pei_data structure by Duncan Laurie · 12 years ago
  91. 53508fe pei_data.h: Fix comment by Marc Jones · 12 years ago
  92. 48a4a7f Provide MRC with a console printing callback function by Vadim Bendebury · 12 years ago
  93. e5a0a5d Initial IGD OpRegion implementation by Stefan Reinauer · 12 years ago
  94. ad67791 Avoid using hardcoded values in MRC cache code by Vadim Bendebury · 12 years ago
  95. a1ea822 Make coreboot use the offset parameter in cbfstool create by Stefan Reinauer · 12 years ago
  96. 4c8027a Make register/value lists const by Stefan Reinauer · 12 years ago
  97. 357bb2d SandyBridge/IvyBridge: Use flash map to find MRC cache by Stefan Reinauer · 12 years ago
  98. c6b9f92 Add missing newline in error message by Stefan Reinauer · 12 years ago
  99. cf81b82 CMOS: Move MRC seed offset into upper bank by Duncan Laurie · 12 years ago
  100. 1e0ddf6 Fix some issues with new "reference" toolchain by Stefan Reinauer · 12 years ago