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review.coreboot.org / coreboot / fbdb085549b6c500e12dc2fb21143a197b4be042 / src / northbridge
  1. fbdb085 intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULT by Kyösti Mälkki · 11 years ago
  2. 15c4ab7 Move select MMCONF_SUPPORT under northbridge by Kyösti Mälkki · 11 years ago
  3. abe6847 Intel GM45, 945, Sandy Bridge: Unify `delay.c` and `udelay.c` by Paul Menzel · 11 years ago
  4. 59158b2 Make setting MAX_PIRQ_LINKs depend on NORTHBRIDGE_VIA_VX900 by Dave Frodin · 11 years ago
  5. 53abac1 amd/cimx/rd890/amd.h: Eliminate redefinition of NULL by Bruce Griffith · 11 years ago
  6. 58fff9d amd/agesa/family15/northbridge.c: Delete unused variable by Bruce Griffith · 11 years ago
  7. 1cc3416 Add support to enable/disable builtin GbE (again) by Stefan Reinauer · 11 years ago
  8. 714212a Revert "Add support to enable/disable builtin GbE" by Kyösti Mälkki · 11 years ago
  9. 8b9d4f3 Vortex86EX northbridge.c : Remove Vortex86DX PCI N/B related code. by Andrew Wu · 11 years ago
  10. 59fb82a intel/sch: Use MMCONF_BASE_ADDRESS by Kyösti Mälkki · 11 years ago
  11. 6aeb4a2 AMD: Drop empty root_complex by Kyösti Mälkki · 11 years ago
  12. 5ce0506 AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM by Rudolf Marek · 11 years ago
  13. 88ebbeb AMD Fam15tn: Add IOMMU BAR allocation to northbridge by Rudolf Marek · 11 years ago
  14. eac00d2 intel/sandybridge: Locate CBMEM TOC early in ramstage by Kyösti Mälkki · 11 years ago
  15. 0651072 Add support for DMP Vortex86EX PCI northbridge. by Andrew Wu · 11 years ago
  16. d358a50 Add support to enable/disable builtin GbE by Stefan Reinauer · 11 years ago
  17. 483ff82 sandybridge: Store MRC cache in CBFS by Patrick Georgi · 11 years ago
  18. 59d0d15 AMD: Kconfig cleanup by Kyösti Mälkki · 11 years ago
  19. 560433b VX900: Use MIN/MAX from stdlib.h instead of redefining them by Alexandru Gagniuc · 11 years ago
  20. 23211b0 VIA VX900: Add minimal ramstage needed to boot linux by Alexandru Gagniuc · 11 years ago
  21. 7d31e7c VX900: Add DDR3 initialization by Alexandru Gagniuc · 11 years ago
  22. 88a3023 VX900: Add support for early romstage by Alexandru Gagniuc · 11 years ago
  23. 7ed7394 i945: Add Display defines for int15h handler. by Denis 'GNUtoo' Carikli · 11 years ago
  24. fd39ddd Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGS by Denis 'GNUtoo' Carikli · 11 years ago
  25. a296ce7 Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture by Ronald G. Minnich · 11 years ago
  26. 7bc35754 AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c" by Christian Gmeiner · 11 years ago
  27. c4e07bb AMD Northbridge LX: convert spd_read_byte() to non-static version by Christian Gmeiner · 11 years ago
  28. e2dc80c AMD Northbridge LX: rename get_systop() to get_top_of_ram() by Christian Gmeiner · 11 years ago
  29. 84ae76c AMD Northbridge LX: include northbridge.h in raminit.c by Christian Gmeiner · 11 years ago
  30. 194ec4d AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-static by Christian Gmeiner · 11 years ago
  31. 6f9f785 AMD Northbridge LX: add some missing includes by Christian Gmeiner · 11 years ago
  32. eb6322f AMD Northbridge LX: make sdram_* function prototypes non-static by Christian Gmeiner · 11 years ago
  33. 29840e2 AMD Fam 15tn: Use all memory on systems with more than 4 GB by Siyuan Wang · 11 years ago
  34. 27435d3 haswell: fix overflow handling TOUUD by Aaron Durbin · 11 years ago
  35. 42409e8 northbridge/amd/amdmct: Use `static const` instead of `const static` by Paul Menzel · 11 years ago
  36. 5750fdd Intel GM45, 945, SNB: Move `multiply_to_tsc()` to `tsc.h` by Ronald G. Minnich · 11 years ago
  37. 51837f9 Intel Sandy Bridge: udelay.c: Change comparison from <= to < by Paul Menzel · 11 years ago
  38. 393619b intel/gm45: Add more debug output to read/write training by Nico Huber · 11 years ago
  39. 12276ac intel/gm45: Handle overflows during DDR3 write training by Nico Huber · 11 years ago
  40. 08bee23 intel/gm45: Refactor DDR3 write training by Nico Huber · 11 years ago
  41. 35e45c0 intel/gm45: Handle overflows during DDR3 read training by Nico Huber · 11 years ago
  42. 26a6435 intel/gm45: Refactor DDR3 read training by Nico Huber · 11 years ago
  43. 0da9286 intel/gm45: Fix interpretation of VT-d disable bit by Nico Huber · 11 years ago
  44. 0f43af2 intel/i5000: Remove unused copy of udelay.c by Nico Huber · 11 years ago
  45. c5e036a Get rid of a number of __GNUC__ checks by Stefan Reinauer · 11 years ago
  46. bed88d6 northbridge/intel/i5000/udelay.c: Remove unused header `console.h` by Paul Menzel · 11 years ago
  47. 3f5f6d8 Drop prototype guarding for romcc by Stefan Reinauer · 11 years ago
  48. 3949e37 Drop CONFIG_AP_CODE_IN_CAR by Stefan Reinauer · 11 years ago
  49. 2a3c106 hardwaremain: drop boot_complete parameter by Stefan Reinauer · 11 years ago
  50. 7cb1ba9 haswell: use tsc for udelay() by Aaron Durbin · 11 years ago
  51. 243aa44 boot: remove cbmem_post_handling() by Aaron Durbin · 11 years ago
  52. 4b213a8 Intel i945: ACPI: Add _OSC method by Denis 'GNUtoo' Carikli · 11 years ago
  53. ed7e29e Lenovo ThinkPad X60: Add Native VGA init. by Denis 'GNUtoo' Carikli · 11 years ago
  54. 8ecec21 Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region" by Nico Huber · 11 years ago
  55. 573a1d6 Persimmon/Fam14/SB800 DSDT: Split into common areas by Mike Loptien · 11 years ago
  56. 1fde22c siemens/sitemp_g1p1: Make ACPI report the right mmconf region by Patrick Georgi · 11 years ago
  57. 5b5cf3d AMD GX1: Remove useless copied header file `northbridge.h` by Paul Menzel · 11 years ago
  58. c6f2722 sandybridge: enable ROM caching by Aaron Durbin · 11 years ago
  59. f567f16 sandybridge: add option to mark graphics memory write-combining. by Aaron Durbin · 11 years ago
  60. fcfe67c haswell: add option to mark graphics memory write-combining. by Aaron Durbin · 11 years ago
  61. bb4e79a x86: add new mtrr implementation by Aaron Durbin · 11 years ago
  62. c965076 resources: introduce reserved_ram_resource() by Aaron Durbin · 11 years ago
  63. c0cbd6e haswell: use dynamic cbmem by Aaron Durbin · 11 years ago
  64. dd4a6d2 coreboot: dynamic cbmem requirement by Aaron Durbin · 11 years ago
  65. 24d1d4b x86: Unify arch/io.h and arch/romcc_io.h by Stefan Reinauer · 11 years ago
  66. 467f31d haswell/lynxpoint: Use new PCH/PM helper functions by Duncan Laurie · 11 years ago
  67. 969ac8d haswell: Drop the device ID check in graphics init path by Duncan Laurie · 11 years ago
  68. 8ce667e haswell: add multipurpose SMM memory region by Aaron Durbin · 12 years ago
  69. bf396ff haswell: use s3_resume field in romstage_handoff by Aaron Durbin · 12 years ago
  70. 605ca1b haswell: cbmem_get_table_location() implementation by Aaron Durbin · 12 years ago
  71. 0013a69 haswell: drop memory reservation for sandybridge GPU bug by Duncan Laurie · 11 years ago
  72. fa91819 AMD Fam15: Add SPD read functions to wrapper code by Kimarie Hoot · 11 years ago
  73. 2ad1dba haswell: move call site of save_mrc_data() by Aaron Durbin · 12 years ago
  74. 9b7f9b9 haswell: remove unused sys_info structure by Aaron Durbin · 12 years ago
  75. 3d0071b haswell: adjust CAR usage by Aaron Durbin · 12 years ago
  76. 21efd8c haswell: fix ACPI MCFG table by Aaron Durbin · 12 years ago
  77. 7af2069 haswell: enable caching before SMM initialization by Aaron Durbin · 12 years ago
  78. 239c2e8 haswell platforms: restructure romstage main by Aaron Durbin · 12 years ago
  79. e6c3b1d haswell: include TSEG region in cacheable memory by Aaron Durbin · 12 years ago
  80. 86a1110 i945: Replace some two magic values by defined names by Patrick Georgi · 11 years ago
  81. 5c66f08 haswell: don't add a 0-sized memory range resource by Aaron Durbin · 12 years ago
  82. 69efaa0 Google Link: Add remaining code to support native graphics by Ronald G. Minnich · 11 years ago
  83. 1570260 haswell: Fix BDSM and BGSM indicies in memory map by Aaron Durbin · 12 years ago
  84. 1fef1f5 haswell: reserve default SMRAM space by Aaron Durbin · 12 years ago
  85. c12ef97 haswell: resource allocation by Aaron Durbin · 12 years ago
  86. 26e7dd7 haswell: more ULT/LP support and minor tweaks by Duncan Laurie · 12 years ago
  87. 7116129 haswell: Add VGA PCI ID mappings by Aaron Durbin · 12 years ago
  88. df7be71 haswell: Add ULT device IDs by Duncan Laurie · 12 years ago
  89. f72ad02 graysreef: update platform information by Aaron Durbin · 12 years ago
  90. 89f79a0 haswell: remove explicit pcie config accesses by Aaron Durbin · 12 years ago
  91. c1989c4 haswell: add PCI id support by Aaron Durbin · 12 years ago
  92. b6b5aa1 haswell: Remove logic to send dram init done to ME by Aaron Durbin · 12 years ago
  93. 30c3900 haswell: notes and updates. by Aaron Durbin · 12 years ago
  94. 8256a9b haswell: align pei_data structure with intel-framework by Aaron Durbin · 12 years ago
  95. b9adf7b haswell: use #defines for constants in udelay.c by Aaron Durbin · 12 years ago
  96. ce36b12 haswell: Add LPT LP device IDs to platform report by Duncan Laurie · 12 years ago
  97. 67113e9 haswell: Update GPU power management setup by Duncan Laurie · 12 years ago
  98. 6d04f0f haswell: always use MMIO PCI config accesses by Aaron Durbin · 12 years ago
  99. 76c3700 haswell: Add initial support for Haswell platforms by Aaron Durbin · 12 years ago
  100. e7ae96f Add Intel Panther Point USB3 initialization by Marc Jones · 12 years ago