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review.coreboot.org / coreboot / 43a1f780ff6809f758092136b0b38c6917c27340 / src / soc / imgtec
  1. e7a336a mips: add coherency argument to identity mapping by Ionela Voinescu · 9 years ago
  2. 90d1235 mainboard/google/urara: change SYS PLL to 700MHz by Ionela Voinescu · 9 years ago
  3. 721f299 imgtec/pistachio: DDR2, DDR3: DLL reset set by Ionela Voinescu · 9 years ago
  4. 6b95406 imgtec/pistachio: DDR2, DDR3: DQS gate early by Ionela Voinescu · 9 years ago
  5. f6d3bd4 imgtec/pistachio: increase CBFS cache by Ionela Voinescu · 9 years ago
  6. c32e80d Drop src/cpu/ indirection for MIPS by Stefan Reinauer · 9 years ago
  7. 2e8d4ed soc/imgtec/pistachio: add implementation for system reset by Ionela Voinescu · 9 years ago
  8. 3bdd45e soc/imgtec/pistachio: Implement hard_reset() by Stefan Reinauer · 9 years ago
  9. a73b931 tree: drop last paragraph of GPL copyright header by Patrick Georgi · 9 years ago
  10. d972f78 linking: link bootblock.elf with .data and .bss sections again by Aaron Durbin · 9 years ago
  11. e5bad5c verstage: use common program.ld for linking by Aaron Durbin · 9 years ago
  12. 60391b6 imgtec/pistachio: remove timestamp_get() implementation by Aaron Durbin · 9 years ago
  13. 6123490 imgtech/pistacho: Add vboot2 memory region by Patrick Georgi · 9 years ago
  14. ba71ca3 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  15. eb22da0e Remove old HAVE_UART_MEMORY_MAPPED select statements by Martin Roth · 9 years ago
  16. 3fa1ad0 pistachio: add DDR3 initialization code by Ionela Voinescu · 9 years ago
  17. 1185c10 pistachio: Use passive windowing as DQS gating scheme by Ionela Voinescu · 9 years ago
  18. 1d4c305 pistachio: sort included header files by Ionela Voinescu · 9 years ago
  19. 11f33e4 pistachio: initialize cbmem area to be empty by Ionela Voinescu · 9 years ago
  20. 4f2f01a pistachio: increase romstage size by Ionela Voinescu · 9 years ago
  21. f4e859b Revert "pistashio: bump up romstage size" by Aaron Durbin · 9 years ago
  22. def0fb5 pistashio: bump up romstage size by Aaron Durbin · 9 years ago
  23. b890a12 Remove address from GPLv2 headers by Patrick Georgi · 9 years ago
  24. e2b0aff Remove Kconfig variable that has no effect by Patrick Georgi · 9 years ago
  25. b4a6ca9 imgtec/pistachio: Add comment on the unusual memory layout by Patrick Georgi · 9 years ago
  26. 6e944c4 imgtech/pistachio: Give some more space to the bootblock by Patrick Georgi · 9 years ago
  27. aae53ab kbuild: automatically include SOCs by Stefan Reinauer · 9 years ago
  28. 5d997f9 imgtec/pistachio: DDR reads return to controller with no bubbles by Ionela Voinescu · 9 years ago
  29. a2c4f9e imgtec/pistachio: DDR row/bank/column mapping by Ionela Voinescu · 9 years ago
  30. 97db1fb soc: select generic gpio lib on (almost) all non-x86 SOCs by Stefan Reinauer · 9 years ago
  31. 11ecdb7 imgtec/pistachio: increase RAM CBFS cache size by Vadim Bendebury · 9 years ago
  32. 823f607 pistachio: Remove 50% DDR bandwidth restriction by Ionela Voinescu · 9 years ago
  33. 51ad6ac pistachio: Decrease DDR ODT from 75R to 50R by Ionela Voinescu · 9 years ago
  34. 59074ff pistachio: clean DDR2 initialization code by Ionela Voinescu · 9 years ago
  35. 38063b0 pistachio: add clock setup for all I2C interfaces by Ionela Voinescu · 9 years ago
  36. b8936ad urara: Identity map DRAM/SRAM by Andrew Bresticker · 9 years ago
  37. 8549797 imgtec/pistachio: Add spi_crop_chunk() by Patrick Georgi · 9 years ago
  38. b116a1a pistachio: Move console UART to a Kconfig variable by David Hendricks · 10 years ago
  39. d6aaca9 pistachio: add DDR2 initialization code by Ionela Voinescu · 10 years ago
  40. 7271e23 pistachio: report UART register width by Vadim Bendebury · 10 years ago
  41. 9dccf1c uart: pass register width in the coreboot table by Vadim Bendebury · 10 years ago
  42. fdce680 pistachio: implement clock setup for I2C0 by Ionela Voinescu · 9 years ago
  43. a702390 pistachio: Fix ROM clock base address by Ionela Voinescu · 9 years ago
  44. 8b1f23e urara: add clock setup for MIPS CPU, ROM and Ethernet by Ionela Voinescu · 10 years ago
  45. 41d1ca8 pistachio: fix clocks setup code by Ionela Voinescu · 10 years ago
  46. b9d59bb pistachio: Use 1.8433179 MHz for UART refclk by David Hendricks · 10 years ago
  47. 30fc667 pistachio: increase size of bootblock to 18 KB by Ionela Voinescu · 10 years ago
  48. 55b8dc0 pistachio: change memory layout as to allow bigger CBFS cache by Ionela Voinescu · 10 years ago
  49. 1c0d0c0 pistachio: spi: use same clock edge for RX and TX by Ionela Voinescu · 10 years ago
  50. b3f666b urara: Configure clocks and MFIOs by Ionela Voinescu · 10 years ago
  51. efcee76 CBFS: Automate ROM image layout and remove hardcoded offsets by Julius Werner · 10 years ago
  52. f9ff353 spi: support controllers with limited transfer size capabilities by Vadim Bendebury · 10 years ago
  53. b9d9615 urara: add support for DMA coherent memory area by Ionela Voinescu · 10 years ago
  54. fb3ea74 pistachio: increase the size of romstage to 36K by Ionela Voinescu · 10 years ago
  55. 420b0f6 pistachio: add timer frequency for SOC; correct platform ID by Ionela Voinescu · 10 years ago
  56. f3bc026 pistachio: add SOC descriptor by Vadim Bendebury · 10 years ago
  57. fe51cc4 pistachio: modify memory layout by Vadim Bendebury · 10 years ago
  58. 40ff8a5 pistachio: set correct CBMEM top address by Vadim Bendebury · 10 years ago
  59. cbc44f7 pistachio: allow more room for bootblock by Vadim Bendebury · 10 years ago
  60. 52a8879 pistachio: implement timer support by Vadim Bendebury · 10 years ago
  61. 0812568 pistachio: Change all SoC headers to <soc/headername.h> system by Julius Werner · 10 years ago
  62. a48ca84 kconfig: drop intermittend forwarder files by Stefan Reinauer · 9 years ago
  63. ec5e5e0 New mechanism to define SRAM/memory map with automatic bounds checking by Julius Werner · 10 years ago
  64. 1d84ef5 pistachio: add gpio type definition by Vadim Bendebury · 10 years ago
  65. 5c9f534 urara: Fix CBFS header definitions by Vadim Bendebury · 10 years ago
  66. 146d05d imgtec/pistachio: Bring uart driver to modern standards by Patrick Georgi · 9 years ago
  67. 8880df1 pistachio: don't open code ramstage loading by Aaron Durbin · 9 years ago
  68. 49aad6b soc/imgtec/pistachio: Add IMGTEC SPI controller driver by Ionela Voinescu · 10 years ago
  69. 2d510d0 urara: use proper SOC name by Vadim Bendebury · 10 years ago
  70. 197b801 mips: fix bootblock stack definitions by Vadim Bendebury · 10 years ago
  71. f16b082 danube: Use the generic timer interface by Vadim Bendebury · 10 years ago
  72. c7b3f72 danube: use SOC specific rom stage code by Vadim Bendebury · 10 years ago
  73. b2e465d danube: prepare SOC directory for urara by Vadim Bendebury · 10 years ago
  74. c1081a4 imgtec/danube: Add support for ImgTec Danube SoC by Paul Burton · 10 years ago