| Angel Pons | 08da24e | 2020-04-03 01:21:24 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| Sergej Ivanov | d777c78 | 2015-04-03 18:10:27 +0300 | [diff] [blame] | 2 | |
| 3 | /* DefinitionBlock Statement */ |
| Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
| Sergej Ivanov | d777c78 | 2015-04-03 18:10:27 +0300 | [diff] [blame] | 5 | DefinitionBlock ( |
| Elyes HAOUAS | 2bfaabc | 2020-10-01 17:03:55 +0200 | [diff] [blame] | 6 | "dsdt.aml", |
| Elyes HAOUAS | 37509d7 | 2020-10-01 17:11:56 +0200 | [diff] [blame] | 7 | "DSDT", |
| Elyes HAOUAS | 90d00de | 2020-10-05 16:38:53 +0200 | [diff] [blame] | 8 | ACPI_DSDT_REV_2, |
| Elyes HAOUAS | 6d19a20 | 2018-11-22 11:15:29 +0100 | [diff] [blame] | 9 | OEM_ID, |
| 10 | ACPI_TABLE_CREATOR, |
| Sergej Ivanov | d777c78 | 2015-04-03 18:10:27 +0300 | [diff] [blame] | 11 | 0x00010001 /* OEM Revision */ |
| 12 | ) |
| 13 | { /* Start of ASL file */ |
| Kyösti Mälkki | cf246d5 | 2021-01-21 08:17:00 +0200 | [diff] [blame] | 14 | #include <acpi/dsdt_top.asl> |
| Sergej Ivanov | d777c78 | 2015-04-03 18:10:27 +0300 | [diff] [blame] | 15 | |
| 16 | /* Globals for the platform */ |
| 17 | #include "acpi/mainboard.asl" |
| 18 | |
| 19 | /* Describe the USB Overcurrent pins */ |
| 20 | #include "acpi/usb_oc.asl" |
| 21 | |
| 22 | /* PCI IRQ mapping for the Southbridge */ |
| 23 | #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> |
| 24 | |
| Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 25 | /* Describe the processor tree (\_SB) */ |
| Sergej Ivanov | d777c78 | 2015-04-03 18:10:27 +0300 | [diff] [blame] | 26 | #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> |
| 27 | |
| 28 | /* Contains the supported sleep states for this chipset */ |
| Kyösti Mälkki | 390ba04 | 2017-08-07 21:42:46 +0300 | [diff] [blame] | 29 | #include <southbridge/amd/common/acpi/sleepstates.asl> |
| Sergej Ivanov | d777c78 | 2015-04-03 18:10:27 +0300 | [diff] [blame] | 30 | |
| 31 | /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ |
| 32 | #include "acpi/sleep.asl" |
| 33 | |
| 34 | /* stuff for sio */ |
| 35 | #include "acpi/flag0.asl" |
| 36 | |
| 37 | /* System Bus */ |
| 38 | Scope(\_SB) { /* Start \_SB scope */ |
| Elyes HAOUAS | 54ec7c8 | 2018-05-28 13:22:35 +0200 | [diff] [blame] | 39 | /* global utility methods expected within the \_SB scope */ |
| Sergej Ivanov | d777c78 | 2015-04-03 18:10:27 +0300 | [diff] [blame] | 40 | #include <arch/x86/acpi/globutil.asl> |
| 41 | |
| 42 | /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ |
| 43 | #include "acpi/routing.asl" |
| 44 | |
| 45 | Device(PWRB) { |
| 46 | Name(_HID, EISAID("PNP0C0C")) |
| 47 | Name(_UID, 0xAA) |
| 48 | Name(_PRW, Package () {3, 0x04}) |
| 49 | Name(_STA, 0x0B) |
| 50 | } |
| 51 | |
| 52 | Device(PCI0) { |
| 53 | /* Describe the AMD Northbridge */ |
| 54 | #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> |
| 55 | |
| 56 | /* Describe the AMD Fusion Controller Hub Southbridge */ |
| 57 | #include <southbridge/amd/agesa/hudson/acpi/fch.asl> |
| 58 | |
| 59 | /* sio fixup */ |
| 60 | #include "acpi/sio.asl" |
| 61 | } |
| 62 | |
| 63 | /* Describe PCI INT[A-H] for the Southbridge */ |
| 64 | #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> |
| 65 | |
| 66 | } /* End \_SB scope */ |
| 67 | |
| 68 | /* Describe SMBUS for the Southbridge */ |
| 69 | #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> |
| 70 | |
| 71 | /* Define the General Purpose Events for the platform */ |
| 72 | #include "acpi/gpe.asl" |
| 73 | |
| 74 | /* Define the Thermal zones and methods for the platform */ |
| 75 | #include "acpi/thermal.asl" |
| 76 | |
| Sergej Ivanov | d777c78 | 2015-04-03 18:10:27 +0300 | [diff] [blame] | 77 | } |
| 78 | /* End of ASL file */ |