| Sergej Ivanov | d777c78 | 2015-04-03 18:10:27 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2013 Sage Electronic Engineering, LLC |
| 6 | * Copyright (C) 2015 Sergej Ivanov <getinaks@gmail.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | /* DefinitionBlock Statement */ |
| 23 | DefinitionBlock ( |
| 24 | "DSDT.AML", /* Output filename */ |
| 25 | "DSDT", /* Signature */ |
| 26 | 0x02, /* DSDT Revision, needs to be 2 for 64bit */ |
| 27 | "AMD ", /* OEMID */ |
| 28 | "COREBOOT", /* TABLE ID */ |
| 29 | 0x00010001 /* OEM Revision */ |
| 30 | ) |
| 31 | { /* Start of ASL file */ |
| 32 | /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ |
| 33 | |
| 34 | /* Globals for the platform */ |
| 35 | #include "acpi/mainboard.asl" |
| 36 | |
| 37 | /* Describe the USB Overcurrent pins */ |
| 38 | #include "acpi/usb_oc.asl" |
| 39 | |
| 40 | /* PCI IRQ mapping for the Southbridge */ |
| 41 | #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> |
| 42 | |
| 43 | /* Describe the processor tree (\_PR) */ |
| 44 | #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> |
| 45 | |
| 46 | /* Contains the supported sleep states for this chipset */ |
| 47 | #include <southbridge/amd/agesa/hudson/acpi/sleepstates.asl> |
| 48 | |
| 49 | /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ |
| 50 | #include "acpi/sleep.asl" |
| 51 | |
| 52 | /* stuff for sio */ |
| 53 | #include "acpi/flag0.asl" |
| 54 | |
| 55 | /* System Bus */ |
| 56 | Scope(\_SB) { /* Start \_SB scope */ |
| 57 | /* global utility methods expected within the \_SB scope */ |
| 58 | #include <arch/x86/acpi/globutil.asl> |
| 59 | |
| 60 | /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ |
| 61 | #include "acpi/routing.asl" |
| 62 | |
| 63 | Device(PWRB) { |
| 64 | Name(_HID, EISAID("PNP0C0C")) |
| 65 | Name(_UID, 0xAA) |
| 66 | Name(_PRW, Package () {3, 0x04}) |
| 67 | Name(_STA, 0x0B) |
| 68 | } |
| 69 | |
| 70 | Device(PCI0) { |
| 71 | /* Describe the AMD Northbridge */ |
| 72 | #include <northbridge/amd/agesa/family16kb/acpi/northbridge.asl> |
| 73 | |
| 74 | /* Describe the AMD Fusion Controller Hub Southbridge */ |
| 75 | #include <southbridge/amd/agesa/hudson/acpi/fch.asl> |
| 76 | |
| 77 | /* sio fixup */ |
| 78 | #include "acpi/sio.asl" |
| 79 | } |
| 80 | |
| 81 | /* Describe PCI INT[A-H] for the Southbridge */ |
| 82 | #include <southbridge/amd/agesa/hudson/acpi/pci_int.asl> |
| 83 | |
| 84 | } /* End \_SB scope */ |
| 85 | |
| 86 | /* Describe SMBUS for the Southbridge */ |
| 87 | #include <southbridge/amd/agesa/hudson/acpi/smbus.asl> |
| 88 | |
| 89 | /* Define the General Purpose Events for the platform */ |
| 90 | #include "acpi/gpe.asl" |
| 91 | |
| 92 | /* Define the Thermal zones and methods for the platform */ |
| 93 | #include "acpi/thermal.asl" |
| 94 | |
| 95 | /* Define the System Indicators for the platform */ |
| 96 | #include "acpi/si.asl" |
| 97 | |
| 98 | } |
| 99 | /* End of ASL file */ |